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31. 发明授权

US07450423B2 Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure 有权
公开(公告)号：US07450423B2
公开(公告)日：2008-11-11
申请号：US11649348
申请日：2007-01-03
申请人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
IPC分类号： G11C11/34 , G11C16/06 , H01L29/94
CPC分类号： H01L29/792 , G11C16/0466 , G11C16/0475 , G11C16/14 , H01L21/28282 , H01L29/4234 , H01L29/513
摘要： A method of operating a memory cell by applying a positive voltage to the gate sufficient to cause hole tunneling from the gate toward the charge storage layer is disclosed. The method is applied to a memory cell including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region. The memory cell also has a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer. The upper insulating multi-layer structure comprises a lower dielectric layer and an upper nitride layer disposed above the lower dielectric layer and the memory cell has a gate disposed above the upper insulating multi-layer structure.

32. 发明授权

US06638879B2 Method for forming nitride spacer by using atomic layer deposition 有权
标题翻译：通过原子层沉积形成氮化物间隔物的方法
公开(公告)号：US06638879B2
公开(公告)日：2003-10-28
申请号：US10003317
申请日：2001-12-06
申请人： Jung-Yu Hsieh , Chin-Hsiang Lin
发明人： Jung-Yu Hsieh , Chin-Hsiang Lin
IPC分类号： H01L21477
CPC分类号： H01L21/0228 , C23C16/345 , C23C16/45525 , H01L21/0217 , H01L21/02211 , H01L21/3141 , H01L21/3185 , H01L29/6659
摘要： The present invention provides a method for forming a silicon nitride spacer by using an atomic layer deposition (ALD) method. The procedure of the ALD is to use a first kind of excess gas as a reactant air and thus produce a first mono-layer solid phase of the first reactant air on the wafer. When the first chemical reaction is completed, the first excess air is drawn out, and then the second excess air is released to deposit a second mono-layer solid phase of the second reactant air on the first mono-layer solid phase. In this way, a whole deposited layer with a layer of the first mono-layer solid phase, a layer of the second mono-layer solid phase, and so on are stepwise formed on the wafer surface. The ALD method is a time consuming task in deposition process such as in the generation of 0.35 &mgr;m to 0.5 &mgr;m of VLSI ages. However, in the generation of 0.18 &mgr;m, 0.13 &mgr;m or beyond of VLSI ages, because the device is getting smaller than ever before, the deposition speed of the ALD method is just right on time to meet the demand and is an appropriate method in depositing silicon nitride spacer.
摘要翻译：本发明提供了通过使用原子层沉积（ALD）方法形成氮化硅间隔物的方法。 ALD的过程是使用第一种过量气体作为反应物空气，从而在晶片上产生第一反应物空气的第一单层固相。当第一化学反应完成时，第一过量空气被抽出，然后第二过量空气被释放，以将第二反应物空气的第二单层固相沉积在第一单层固相上。以这种方式，在晶片表面上逐步形成具有第一单层固相层，第二单层固相层等的全部沉积层。 ALD方法在沉积过程中是耗时的任务，例如在0.35m至0.5mil的VLSI年龄的产生中。但是，由于器件比以往任何时候都要小，所以在0.18微米，0.13微米或超过VLSI的时代，ALD方法的沉积速度正好准时满足需求，是一种适当的方法氮化硅间隔物。

33. 发明授权

US08026136B2 Methods of forming low hydrogen concentration charge-trapping layer structures for non-volatile memory 有权
标题翻译：形成用于非挥发性记忆体的低氢浓度电荷捕获层结构的方法
公开(公告)号：US08026136B2
公开(公告)日：2011-09-27
申请号：US11964322
申请日：2007-12-26
申请人： Yen-Hao Shih , Min-Ta Wu , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Yen-Hao Shih , Min-Ta Wu , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/8238 , H01L21/311
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513 , H01L29/518
摘要： Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.
摘要翻译：存储单元包括：半导体衬底，具有由沟道区分开的至少两个源极/漏极区域; 设置在通道区域上方的电荷捕获结构; 以及设置在电荷捕获结构上方的栅极; 其中所述电荷捕获结构包括底部绝缘层，第一电荷俘获层和第二电荷俘获层，其中所述底部绝缘层和所述基底之间的界面的氢浓度小于约3×1011 / cm -2，以及形成这种记忆单元的方法。

34. 发明授权

US07763935B2 ONO formation of semiconductor memory device and method of fabricating the same 有权
标题翻译： ONO形成半导体存储器件及其制造方法
公开(公告)号：US07763935B2
公开(公告)日：2010-07-27
申请号：US11159269
申请日：2005-06-23
申请人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833
摘要： A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.
摘要翻译：一种制造非易失性存储器件的方法至少包括以下步骤。首先，提供形成有底部电介质层的基板。然后，通过底部电介质层将杂质引入衬底，以在衬底上形成多个间隔开的掺杂区域。该结构被热退火以推动间隔开的掺杂区域向外扩散。退火后，在底部电介质层上形成电荷捕捉层，在电荷捕获层上形成顶部电介质层。最后，在顶部电介质层上形成栅极结构（如多晶硅层和硅化物）。

35. 发明申请

US20100178758A1 METHODS FOR FABRICATING DIELECTRIC LAYER AND NON-VOLATILE MEMORY 审中-公开
标题翻译：用于制造介电层和非易失性存储器的方法
公开(公告)号：US20100178758A1
公开(公告)日：2010-07-15
申请号：US12354602
申请日：2009-01-15
申请人： Jeng-Hwa Liao , Jung-Yu Hsieh , Ling-Wu Yang
发明人： Jeng-Hwa Liao , Jung-Yu Hsieh , Ling-Wu Yang
IPC分类号： H01L21/443 , H01L21/28
CPC分类号： H01L21/28202 , H01L21/0214 , H01L21/02211 , H01L21/02271 , H01L21/3145 , H01L29/40117
摘要： The method for fabricating the dielectric layer of the present invention is described as follows. A substrate is provided in a chamber, wherein the chamber is a single-wafer LPCVD chamber. A silicon source gas, an oxidation source gas and a nitridation source gas are then introduced into the chamber, wherein a volumetric flow rate ratio of the oxidation source gas to a total amount of the oxidation source gas and the nitridation source gas is varied within a range of 0.0245 to 0.375. Afterwards, the dielectric layer with a dielectric constant within a range of 4.8 to 7.6 is formed on the substrate.
摘要翻译：本发明的电介质层的制造方法如下所述。衬底设置在腔室中，其中腔室是单晶片LPCVD室。然后将硅源气体，氧化源气体和氮化源气体引入室中，其中氧化源气体与氧化源气体和氮化源气体的总量的体积流量比在范围为0.0245至0.375。之后，在基板上形成介电常数为4.8〜7.6的介质层。

36. 发明申请

US20080099826A1 Non-volatile memory cells having a polysilicon-containing, multi-layer insulating structure, memory arrays including the same and methods of operating the same 有权
标题翻译：具有含多晶硅的多层绝缘结构的非易失性存储单元，包括其的存储器阵列及其操作方法
公开(公告)号：US20080099826A1
公开(公告)日：2008-05-01
申请号：US11588830
申请日：2006-10-27
申请人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , G11C16/0466 , H01L29/513 , H01L29/66833 , H01L29/792
摘要： Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material layer interposed between a first dielectric layer and a second dielectric layer; and a gate disposed above the upper insulating multi-layer structure are described along with arrays thereof and methods of operation.
摘要翻译：存储单元包括具有至少两个源极/漏极区域的半导体层，所述源极/漏极区域设置在半导体层的表面下方并被沟道区域分隔开; 设置在通道区域上方的下绝缘层; 电荷存储层，其设置在所述下绝缘层的上方; 上部绝缘多层结构，其设置在所述电荷存储层上方，其中所述上部绝缘多层结构包括介于第一介电层和第二介电层之间的多晶硅材料层; 并且设置在上绝缘多层结构上方的栅极及其阵列及其操作方法。

37. 发明申请

US20080025087A1 METHOD FOR FABRICATING CHARGE-TRAPPING MEMORY 有权
标题翻译：用于制造电荷捕获存储器的方法
公开(公告)号：US20080025087A1
公开(公告)日：2008-01-31
申请号：US11460497
申请日：2006-07-27
申请人： Yen-Hao Shih , Jung-Yu Hsieh , Yi-Lin Yang , Chia-Hua Chang , Jenn-Gwo Hwu
发明人： Yen-Hao Shih , Jung-Yu Hsieh , Yi-Lin Yang , Chia-Hua Chang , Jenn-Gwo Hwu
IPC分类号： G11C16/04
CPC分类号： H01L21/76838 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a charge-trapping memory device is provided. This method includes forming a stacked structure having at least a charge-trapping medium. An annealing process in a hydrogen gas is then performed on the stacked structure subsequent to the device fabrication process. The annealing process is conducted at a temperature of about 350° C. to 450° C. and with the concentration of the hydrogen gas greater than 0.5 mole percent.
摘要翻译：提供了一种电荷俘获存储器件的制造方法。该方法包括形成至少具有电荷捕获介质的堆叠结构。然后在器件制造过程之后对堆叠结构进行氢气中的退火处理。退火过程在约350℃至450℃的温度下进行，氢气的浓度大于0.5摩尔％。

38. 发明授权

US07118968B2 Method for manufacturing interpoly dielectric 有权
标题翻译：多聚电介质的制造方法
公开(公告)号：US07118968B2
公开(公告)日：2006-10-10
申请号：US10919921
申请日：2004-08-17
申请人： Jung-Yu Hsieh
发明人： Jung-Yu Hsieh
IPC分类号： H01L21/8247
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/513
摘要： Roughly described, a floating gate memory cell is fabricated by forming an oxide-nitride dielectric layer above a floating gate of the memory cell and in an oxide growth region not above a floating gate. The nitride layer is removed in the oxide growth region using a mask that protects the nitride layer above the floating gate, and then the bottom oxide layer is removed in the oxide growth region using a wet etch that does not affect the nitride remaining above the floating gate. First and second oxide layers are then formed both above the floating gate and in the oxide growth region, to act as the top layer of ONO above the floating gate and as the gate oxide in the oxide growth region. One of the first and second oxide layers is formed using in-situ steam generation.
摘要翻译：粗略地描述，通过在存储器单元的浮动栅极上方和不在浮动栅极上方的氧化物生长区域中形成氧化物 - 氮化物电介质层来制造浮动栅极存储单元。在氧化物生长区域中使用保护氮化物层的掩模在氧化物生长区域中去除氮化物层，然后在氧化物生长区域中去除底部氧化物层，使用湿蚀刻，该蚀刻不会影响浮在浮动栅极上方的氮化物门。然后在浮置栅极上方和氧化物生长区域中形成第一和第二氧化物层，以在浮栅上方作为ONO的顶层，并且作为氧化物生长区域中的栅极氧化物。第一和第二氧化物层中的一个是使用原位蒸汽产生形成的。

39. 发明授权

US06536130B1 Overlay mark for concurrently monitoring alignment accuracy, focus, leveling and astigmatism and method of application thereof 有权
标题翻译：叠加标记，用于同时监测对准精度，对焦，调平和散光及其应用方法
公开(公告)号：US06536130B1
公开(公告)日：2003-03-25
申请号：US09998286
申请日：2001-11-30
申请人： Te-Hung Wu , Jung-Yu Hsieh , Hsiu-Man Chang
发明人： Te-Hung Wu , Jung-Yu Hsieh , Hsiu-Man Chang
IPC分类号： G01B1100
CPC分类号： G03F7/70633 , G03F7/70641 , Y10S414/136
摘要： An overlay mark for concurrently monitoring alignment accuracy, focus, leveling and astigmatism and a method of application thereof are disclosed. The overlay mark comprises four inner bars and four outer bars formed at the corners of exposure areas. The inner bar has a sawtooth area and a bar-shaped area, and the outer bar is a fore-layer etched pattern. Both the inner bars and the outer bars are formed into rectangles, and each bar is one side of a rectangle and none of the sides are connected. The sawtooth areas of the inner bars disposed on opposite sides are located at a same position. The rectangle formed by the outer bars encloses the rectangle formed by the inner bars. During the monitoring process, a testing beam scans across a scan area being divided into two areas, i.e., one being the outer bars and the sawtooth area of the inner bars, and the other one being the outer bars and the bar-shaped area of the inner bars.
摘要翻译：公开了一种用于同时监视对准精度，对焦，调平和散光的重叠标记及其应用方法。覆盖标记包括形成在曝光区域的角部的四个内部条和四个外部条。内侧杆具有锯齿形区域和棒状区域，外侧杆是前层蚀刻图案。内杆和外杆都形成矩形，并且每个杆是矩形的一侧，并且没有一个侧面连接。设置在相对侧的内侧杆的锯齿区域位于相同位置。由外杆形成的矩形包围由内条形成的矩形。在监视过程中，测试光束扫描扫描区域被划分为两个区域，即一个是内部条的外部条和锯齿形区域，另一个是外部条和条形区域内条。

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