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31. 发明申请

US20120148942A1 DIAGONAL INTERCONNECT FOR IMPROVED PROCESS MARGIN WITH OFF-AXIS ILLUMINATION 审中-公开
标题翻译：用于改进过程亮度的对角线互连与非轴向照明
公开(公告)号：US20120148942A1
公开(公告)日：2012-06-14
申请号：US12966252
申请日：2010-12-13
申请人： James Walter Blatchford
发明人： James Walter Blatchford
IPC分类号： G03F1/00 , G03F7/00
CPC分类号： G03F7/70091 , G03F7/70433
摘要： Mask or reticle methods and structures having pattern feature segments formed at oblique angles to each other. When illuminated using off-axis illumination techniques, a mask or reticle according to the present teachings can result in a more accurately reproduced feature within a photosensitive layer.
摘要翻译：掩模或掩模版方法和结构具有以彼此成倾斜角度形成的图案特征段。当使用离轴照明技术照明时，根据本教导的掩模或掩模版可以在感光层内产生更准确地再现的特征。

32. 发明授权

US08138074B1 ICs with end gates having adjacent electrically connected field poly 有权
标题翻译：具有端栅的IC具有相邻的电连接场聚
公开(公告)号：US08138074B1
公开(公告)日：2012-03-20
申请号：US12939738
申请日：2010-11-04
申请人： James Walter Blatchford
发明人： James Walter Blatchford
IPC分类号： H01L21/00
CPC分类号： H01L27/0207 , Y10S257/901
摘要： A method of forming an IC includes forming a first and a second gate portion using a poly mask. The first portion includes a first active poly gate having a line width W1 over an end of a first active area framed by a first active area edge and a first adjacent active field poly feature having a line width 0.8W1 to 1.3W1 in a first field region. The first field poly feature has a horizontal portion and a first extension portion along a gate width direction extending over the first active area edge having a first minimum spacing (S1). The second gate portion includes a second active poly gate over an end of a second active area framed by a second active area edge electrically connected to a second field poly feature in a second field region having a horizontal portion and a second extension portion along a gate width direction extending over the second active area edge having a second minimum spacing (S2). A dummy field poly feature is between the second active poly gate and the second field poly feature. S1≧1.25S2.
摘要翻译：一种形成IC的方法包括使用聚合掩模形成第一和第二栅极部分。第一部分包括第一有源多晶硅栅极，第一有源多晶硅栅极在第一有源区边缘构成的第一有源区的端部上具有线宽度W1，第一有源多晶硅栅极在第一场中具有线宽0.8W1至1.3W1的第一相邻有源场多晶硅特征地区。第一场多晶体特征具有沿着栅极宽度方向的水平部分和第一延伸部分，该第一延伸部分在第一有效区域边缘上延伸，具有第一最小间距（S1）。第二栅极部分包括在第二有源区域的端部上的第二有源多晶硅栅极，该第二有源区域由第二有源区域边缘构成，第二有源区域边缘电连接到具有水平部分的第二场区域中的第二场多晶体特征，以及沿栅极的第二延伸部分宽度方向在第二有效区域边缘上延伸，具有第二最小间隔（S2）。第二有源多晶硅栅极和第二场多晶硅层之间的虚场多晶硅特征。 S1≥1.25S2。

33. 发明申请

US20100167484A1 Gate line edge roughness reduction by using 2P/2E process together with high temperature bake 有权
标题翻译：通过使用2P / 2E工艺与高温烘烤进行栅极边缘粗糙度降低
公开(公告)号：US20100167484A1
公开(公告)日：2010-07-01
申请号：US12648802
申请日：2009-12-29
申请人： Yiming Gu , James Walter Blatchford
发明人： Yiming Gu , James Walter Blatchford
IPC分类号： H01L21/8234 , H01L21/28 , H01L21/3205 , G03F7/20
CPC分类号： H01L21/28123 , H01L21/32139
摘要： A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.
摘要翻译：图案化多个多晶硅结构的方法包括在半导体本体上形成多晶硅层，并使用减少线边缘粗糙度（LER）的第一图案化工艺来图案化多晶硅层以形成第一多晶硅结构。该方法还包括使用在执行第一图案化工艺之后与第一图案化工艺不同的第二图案化工艺来图案化多晶硅层以形成第二多晶硅结构。

34. 发明授权

US08607170B2 Perturbational technique for co-optimizing design rules and illumination conditions for lithography process 有权
标题翻译：用于光刻工艺共同优化设计规则和照明条件的扰动技术
公开(公告)号：US08607170B2
公开(公告)日：2013-12-10
申请号：US13410088
申请日：2012-03-01
申请人： James Walter Blatchford
发明人： James Walter Blatchford
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F7/70125 , G03F7/70433
摘要： A process of generating design rules, OPC rules and optimizing illumination source models for an integrated circuit layout, to form short lines, terminated lines and crossovers between adjacent parallel route tracks, may include the steps of generating a set of template structures which use a set of characteristic design rules, and performing a plurality of source mask optimization (SMO) operations on the set of template structures with different values for the design rules in each SMO operation. In a first embodiment, the SMO operations are run using a predetermined set of values for each of the design rules, spanning a desired range of design rule values. In a second embodiment, the SMO operations are performed in a conditional iterative process in which values of the design rules are adjusted after each iteration based on results of the iteration.
摘要翻译：产生设计规则，OPC规则和优化用于集成电路布局的照明源模型以在相邻并行路径轨道之间形成短线，终止线和交叉的过程可以包括以下步骤：生成使用集合的模板结构集合的特征设计规则，并且在每个SMO操作中对于设计规则具有不同值的模板结构集合执行多个源掩码优化（SMO）操作。在第一实施例中，使用针对每个设计规则的预定值来运行SMO操作，跨越期望的设计规则值范围。在第二实施例中，在条件迭代过程中执行SMO操作，其中基于迭代结果在每次迭代之后调整设计规则的值。

35. 发明授权

US08461038B2 Two-track cross-connects in double-patterned metal layers using a forbidden zone 有权
标题翻译：使用禁区的双图案金属层中的双轨交叉连接
公开(公告)号：US08461038B2
公开(公告)日：2013-06-11
申请号：US13410236
申请日：2012-03-01
申请人： James Walter Blatchford
发明人： James Walter Blatchford
IPC分类号： H01L21/3213 , H01L21/4763 , H01L21/28
CPC分类号： H01L23/528 , G03F7/0035 , G03F7/70466 , H01L21/0274 , H01L21/31144 , H01L21/76816 , H01L21/76838 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is formed by forming a first interconnect pattern in parallel route tracks, and forming a second interconnect pattern in alternating parallel route tracks. The first interconnect pattern includes a first lead pattern in the parallel route tracks, and the second interconnect pattern includes a second lead pattern in an immediately adjacent route track. The first interconnect pattern includes a crossover pattern which extends from the first lead pattern to the second lead pattern. An exclusion zone in the route track immediately adjacent to the crossover pattern is free of a lead pattern for a lateral distance of two to three times the width of the crossover pattern. Metal interconnect lines are form in the first interconnect pattern and the second interconnect pattern areas, including a continuous metal crossover line through the crossover pattern area. The exclusion zone is free of the metal interconnect lines.
摘要翻译：通过在并行路径轨道中形成第一互连图案并且在交替的平行路径轨道中形成第二互连图案来形成集成电路。第一互连图案包括平行路径轨道中的第一引线图案，并且第二互连图案包括紧邻的路线轨道中的第二引线图案。第一互连图案包括从第一引线图案延伸到第二引线图案的交叉图案。紧邻交叉图案的路径轨道中的排除区域不具有横跨距离为交叉图案的宽度的2至3倍的横向距离的引线图案。金属互连线形成在第一互连图案和第二互连图案区域中，包括通过交叉图案区域的连续金属交叉线。排除区域不含金属互连线。

36. 发明授权

US08455180B2 Gate CD control using local design on both sides of neighboring dummy gate level features 有权
标题翻译： Gate CD控制采用局部设计，在相邻虚拟门级功能的两侧
公开(公告)号：US08455180B2
公开(公告)日：2013-06-04
申请号：US12915974
申请日：2010-10-29
申请人： James Walter Blatchford , Yong Seok Choi , Thomas J. Aton
发明人： James Walter Blatchford , Yong Seok Choi , Thomas J. Aton
IPC分类号： G03F7/20
CPC分类号： G03F7/20 , G03F1/36 , G03F1/38 , G06F17/50 , G06F17/5068 , H01L21/28123
摘要： A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8W1 to 1.3W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ≧2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.
摘要翻译：形成包括MOS晶体管的IC的方法包括使用栅极掩模形成在有源区上具有线宽度W1的第一有源栅极特征和具有线宽0.8W1至1.3W1的相邻虚拟特征。相邻的虚拟特征具有与第一有效栅极特征相邻的第一侧和与第一侧相对的第二侧上的最近的栅极级特征。相邻的虚拟特征基于到第一有源栅极特征的距离来限定栅极间距，或者相邻的虚设特征维持包括第一有源栅极特征的栅极阵列中的栅极间距。相邻虚拟特征和最近的门级特征之间的间隔（i）维持栅极间距，或（ii）提供> = 2倍栅极间距的SRAF使能距离，并且栅极掩模包括在SRAF距离上的SRAF。

37. 发明申请

US20120223439A1 TWO-TRACK CROSS-CONNECT IN DOUBLE-PATTERNED STRUCTURE USING RECTANGULAR VIA 有权
标题翻译：使用矩形横截面的双曲线结构中的双轨交叉连接
公开(公告)号：US20120223439A1
公开(公告)日：2012-09-06
申请号：US13410241
申请日：2012-03-01
申请人： James Walter Blatchford , Scott William Jessen
发明人： James Walter Blatchford , Scott William Jessen
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76816 , H01L21/76838 , H01L21/76895 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.
摘要翻译：可以通过在第一多个平行路径轨道中形成第一互连图案并且在第二多个平行路径轨道中形成第二互连图案来形成集成电路，其中第二多个路线轨道与第一多个平行路线轨道交替的路线。第一互连图案包括第一引线图案，并且第二互连图案包括第二引线图案，使得包含第一引线图案的路径轨道紧邻包含第二引线图案的路径轨迹。金属互连线形成在第一互连图案和第二互连图案中。拉伸交叉连接形成在仅连接第一引线和第二引线的垂直连接电平，例如通孔或接触电平。拉伸交叉连接与其他垂直互连元件同时形成。

38. 发明申请

US20120107729A1 GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUMMY GATE LEVEL FEATURES 有权
标题翻译：使用本地设计的GATE CD控制在相邻的两个门的水平特征
公开(公告)号：US20120107729A1
公开(公告)日：2012-05-03
申请号：US12915974
申请日：2010-10-29
申请人： James Walter Blatchford , Yong Seok Choi , Thomas J. Aton
发明人： James Walter Blatchford , Yong Seok Choi , Thomas J. Aton
IPC分类号： G03F1/00 , H01L21/336 , G06F17/50
CPC分类号： G03F7/20 , G03F1/36 , G03F1/38 , G06F17/50 , G06F17/5068 , H01L21/28123
摘要： A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8W1 to 1.3W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ≧2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.
摘要翻译：形成包括MOS晶体管的IC的方法包括使用栅极掩模形成在有源区上具有线宽度W1的第一有源栅极特征和具有线宽0.8W1至1.3W1的相邻虚拟特征。相邻的虚拟特征具有与第一有效栅极特征相邻的第一侧和与第一侧相对的第二侧上的最近的栅极级特征。相邻的虚拟特征基于到第一有源栅极特征的距离来限定栅极间距，或者相邻的虚设特征维持包括第一有源栅极特征的栅极阵列中的栅极间距。相邻的虚拟特征与最近的栅极电平特征（i）之间的间隔保持栅极间距，或（ii）提供比栅极间距大2倍的SRAF使能距离，并且栅极掩模包括在SRAF距离上的SRAF。

39. 发明申请

US20120091531A1 Flexible Integration of Logic Blocks with Transistors of Different Threshold Voltages 有权
标题翻译：逻辑块与不同阈值电压晶体管的灵活集成
公开(公告)号：US20120091531A1
公开(公告)日：2012-04-19
申请号：US12904918
申请日：2010-10-14
申请人： Gregory Charles Baldwin , James Walter Blatchford, JR.
发明人： Gregory Charles Baldwin , James Walter Blatchford, JR.
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/823807 , H01L27/0207
摘要： An integrated circuit constructed according to an arrangement of logic blocks, with one or more logic blocks including transistors of a different threshold voltage than in other logic blocks. Spacing between neighboring active regions of different threshold voltages is minimized by constraining the angle of implant for the threshold adjust implant, and by constraining the thickness of the mask layer used with that implant. These constraints ensure adequate implant of dopant into the channel region while blocking the implant into channel regions not subject to the threshold adjust, while avoiding shadowing from the mask layer. Efficiency is attained by constraining the direction of implant to substantially perpendicular to the run of the gate electrodes in the implanted regions.
摘要翻译：根据逻辑块的布置构造的集成电路，其中一个或多个逻辑块包括不同于其它逻辑块的阈值电压的晶体管。通过限制用于阈值调整植入物的植入角度，并通过约束与该植入物一起使用的掩模层的厚度，使不同阈值电压的相邻有效区域之间的间距最小化。这些约束确保掺杂剂充分注入沟道区，同时阻止植入物进入不经过阈值调整的通道区，同时避免掩模从掩模层的遮蔽。通过将注入的方向约束到植入区域中的栅电极的行程基本垂直来实现效率。

40. 发明授权

US07807343B2 EDA methodology for extending ghost feature beyond notched active to improve adjacent gate CD control using a two-print-two-etch approach 有权
标题翻译： EDA方法，用于将重影特征扩展到缺口活动之外，以使用双印双蚀刻方法来改善相邻门CD控制
公开(公告)号：US07807343B2
公开(公告)日：2010-10-05
申请号：US11621605
申请日：2007-01-10
申请人： Benjamen Michael Rathsack , James Walter Blatchford
发明人： Benjamen Michael Rathsack , James Walter Blatchford
IPC分类号： G03C5/00 , G03F1/00 , G03F7/00
CPC分类号： H01L21/32139 , G03F1/36 , G03F1/70
摘要： In accordance with various embodiments, semiconductor devices and methods of forming semiconductor devices having non-rectangular active regions are provided. An exemplary method includes using a first mask to form a plurality of first features over a non-rectangular shaped active region and at least one ghost feature, wherein the plurality of first features extend beyond an edge of the non-rectangular shaped active region. The method further includes using a second mask to remove a portion of the plurality of first features extending beyond the edge of the non-rectangular shaped active region and the at least one ghost feature.
摘要翻译：根据各种实施例，提供了形成具有非矩形有源区域的半导体器件的半导体器件和方法。示例性方法包括使用第一掩模在非矩形形状的有源区域和至少一个重影特征上形成多个第一特征，其中多个第一特征延伸超过非矩形形状的有源区域的边缘。该方法还包括使用第二掩模去除延伸超过非矩形有源区域和至少一个重影特征的边缘的多个第一特征的一部分。

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