专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07936620B2 Receiver of semiconductor memory apparatus 有权
标题翻译：半导体存储器的接收器
公开(公告)号：US07936620B2
公开(公告)日：2011-05-03
申请号：US12483413
申请日：2009-06-12
申请人： Tae-Jin Hwang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Tae-Jin Hwang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1084
摘要： A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.
摘要翻译：半导体存储装置的接收器包括：第一输入晶体管，其配置为当输入信号等于或大于预定电平时导通; 配置为当输入信号等于或小于预定电平时导通的第二输入晶体管; 第一输出节点电压控制单元，被配置为当所述第一输入晶体管导通时增加输出节点的电压电平; 第二输出节点电压控制单元，被配置为当所述第二输入晶体管导通时降低所述输出节点的电压电平; 第三输入晶体管，被配置为当所述输入信号的反相信号等于或小于所述预定电压电平时，增加所述输出节点的电压电平; 以及第四输入晶体管，被配置为当输入信号的反相信号等于或大于预定电压电平时降低输出节点的电压电平。

32. 发明授权

US07863957B2 Duty cycle correction circuit and semiconductor integrated circuit apparatus including the same 有权
标题翻译：占空比校正电路和包括其的半导体集成电路装置
公开(公告)号：US07863957B2
公开(公告)日：2011-01-04
申请号：US12331294
申请日：2008-12-09
申请人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
发明人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
IPC分类号： H03K5/04
CPC分类号： H03K5/1565 , H03K5/151 , H03K2005/00058
摘要： A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.
摘要翻译：占空比校正电路包括：相位分离器，被配置为控制DLL时钟信号的相位以产生上升时钟信号和下降时钟信号;时钟延迟单元，被配置为响应于时钟信号延迟上升时钟信号和下降时钟信号控制信号以产生延迟的上升时钟信号和延迟的下降时钟信号，占空比校正单元，被配置为产生校正上升时钟信号和校正下降时钟信号，该时钟信号响应于延迟的上升时钟信号的边沿定时而触发，延迟下降时钟信号，以及延迟控制单元，被配置为检测校正上升时钟信号和校正下降时钟信号的占空比，以产生控制信号。

33. 发明申请

US20090231007A1 SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF OVERCOMING CLOCK SIGNAL JITTER 失效
标题翻译：半导体集成电路可以覆盖时钟信号抖动
公开(公告)号：US20090231007A1
公开(公告)日：2009-09-17
申请号：US12330287
申请日：2008-12-08
申请人： Ic Su Oh , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Ic Su Oh , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03K7/02
CPC分类号： H03K5/133 , H03K5/003 , H03K5/156
摘要： A semiconductor integrated circuit includes a voltage supplying unit that supplies a first regulated voltage and a second regulated voltage by using a first reference voltage and a second reference voltage, respectively, and a clock buffer unit that supplies an output clock clocking within a range of the first regulated voltage and the second regulated voltage.
摘要翻译：一种半导体集成电路包括分别通过使用第一参考电压和第二参考电压来提供第一调节电压和第二调节电压的电压提供单元，以及时钟缓冲器单元，其提供在第一调节电压和第二调节电压。

34. 发明申请

US20090206900A1 DUTY CYCLE CORRECTION CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE 审中-公开
标题翻译：占空比校正电路和校正周期的方法
公开(公告)号：US20090206900A1
公开(公告)日：2009-08-20
申请号：US12168560
申请日：2008-07-07
申请人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Jae Min Jang , Hyung Soo Kim , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
发明人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Jae Min Jang , Hyung Soo Kim , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
IPC分类号： H03K3/017
CPC分类号： G11C8/04 , H03K5/1565 , H03K2217/0018
摘要： A duty cycle correction circuit capable of reducing current consumption and that includes a back-bias voltage supply circuit for supplying back-bias voltages, wherein a duty cycle of an input clock is reflected on the back-bias voltages; and a buffer for adjusting the duty cycle of the input clock and configured to receive the back-bias voltages.
摘要翻译：一种能够降低电流消耗的占空比校正电路，包括用于提供反向偏置电压的反向偏置电压供给电路，其中输入时钟的占空比反映在反向偏置电压上; 以及用于调整输入时钟的占空比并被配置为接收反偏压的缓冲器。

35. 发明授权

US09201415B2 Internal control signal regulation circuit 有权
标题翻译：内部控制信号调节电路
公开(公告)号：US09201415B2
公开(公告)日：2015-12-01
申请号：US13341682
申请日：2011-12-30
申请人： Yong Ju Kim , Dae Han Kwon , Hae Rang Choi , Jae Min Jang
发明人： Yong Ju Kim , Dae Han Kwon , Hae Rang Choi , Jae Min Jang
IPC分类号： H03K19/00 , G05B19/042
CPC分类号： G05B19/042 , G05B2219/23314 , G05B2219/24036 , G05B2219/24037
摘要： An internal control signal regulation circuit includes a programming test unit configured to detect an internal control signal in response to an external control signal and generate a selection signal, test codes and a programming enable signal; and a code processing unit configured to receive the test codes or programming codes in response to the selection signal and regulate the internal control signal.
摘要翻译：内部控制信号调节电路包括：编程测试单元，被配置为响应于外部控制信号检测内部控制信号，并产生选择信号，测试代码和编程使能信号; 以及代码处理单元，被配置为响应于所述选择信号接收所述测试代码或编程代码并调节所述内部控制信号。

36. 发明授权

US08436666B2 Interface apparatus for semiconductor integrated circuit and interfacing method thereof 有权
标题翻译：半导体集成电路接口装置及其接口方法
公开(公告)号：US08436666B2
公开(公告)日：2013-05-07
申请号：US12650122
申请日：2009-12-30
申请人： Ji-Wang Lee , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang Lee , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03K19/0175 , H03K5/1565
摘要： An interface apparatus for a semiconductor integrated circuit and an interfacing method thereof controls the VOX of differential signals to a target level in response to the differential signals being outputted by an output block. The interface apparatus for a semiconductor integrated circuit includes an output block configured to output differential signals output by an internal circuit a detector configured to detect a timing error of the differential signals; and a controller configured to control a timing of the differential signals output by the internal circuit according to a detection result of the detector.
摘要翻译：半导体集成电路的接口装置及其接口方法响应于由输出块输出的差分信号，将差分信号的VOX控制到目标电平。用于半导体集成电路的接口装置包括：输出块，被配置为输出由内部电路输出的差分信号;检测器，被配置为检测差分信号的定时误差; 以及控制器，被配置为根据检测器的检测结果来控制由内部电路输出的差分信号的定时。

37. 发明申请

US20130099838A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME 有权
标题翻译：半导体集成电路及其驱动方法
公开(公告)号：US20130099838A1
公开(公告)日：2013-04-25
申请号：US13334241
申请日：2011-12-22
申请人： Yong-Ju Kim , Dae-Han Kwon , Hae-Rang Choi , Jae-Min Jang
发明人： Yong-Ju Kim , Dae-Han Kwon , Hae-Rang Choi , Jae-Min Jang
IPC分类号： H03L7/095
CPC分类号： H03L7/0814 , G11C7/222 , G11C11/40 , G11C29/023 , G11C2029/0409
摘要： A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.
摘要翻译：半导体集成电路包括：延迟锁定环（DLL），被配置为通过将源时钟信号延迟第一延迟时间来获得锁定来产生DLL时钟信号，其中响应于更新来控制DLL的更新周期锁定后的周期控制信号完成; 以及更新周期控制器，被配置为响应于源时钟信号和从DLL提供的多个控制信号，基于在DLL的循环路径中出现的第二延迟时间来生成更新周期控制信号。

38. 发明授权

US08410836B2 Phase locked loop 有权
标题翻译：锁相环
公开(公告)号：US08410836B2
公开(公告)日：2013-04-02
申请号：US12916901
申请日：2010-11-01
申请人： Hae-Rang Choi , Yong-Ju Kim , Jae-Min Jang
发明人： Hae-Rang Choi , Yong-Ju Kim , Jae-Min Jang
IPC分类号： H03L7/06
CPC分类号： H03L7/14 , H03L7/113
摘要： A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal.
摘要翻译：锁相环包括相位检测器，被配置为将输入时钟的相位与反馈时钟的相位进行比较以产生相位比较结果，初始频率值提供器被配置为检测输入时钟的频率并提供频率检测结果，配置为基于相位比较结果和频率检测结果产生频率控制信号的控制器，以及响应于频率控制信号产生输出时钟的振荡器。

39. 发明申请

US20130043901A1 ON-DIE TERMINATION CIRCUIT 有权
标题翻译：端子终止电路
公开(公告)号：US20130043901A1
公开(公告)日：2013-02-21
申请号：US13657123
申请日：2012-10-22
申请人： Yong Ju KIM , Hyung Soo KIM , Hae Rang CHOI , Jae Min JANG
发明人： Yong Ju KIM , Hyung Soo KIM , Hae Rang CHOI , Jae Min JANG
IPC分类号： H03K17/16
CPC分类号： H04L25/0298
摘要： An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.
摘要翻译：片上终端电路包括：参考周期信号生成电路，其根据参考电压的电平生成基准周期信号;第一周期信号生成电路，其根据电压的电平生成第一周期信号; 周期比较电路，其将第一周期信号的周期与基准周期信号的周期进行比较，并计数多个驱动信号;以及驱动器电路，其响应于多个驱动信号而驱动该焊盘。

40. 发明申请

US20120268180A1 DELAY LOCKED LOOP 有权
标题翻译：延迟锁定环
公开(公告)号：US20120268180A1
公开(公告)日：2012-10-25
申请号：US13190841
申请日：2011-07-26
申请人： Jae-Min JANG , Yong-Ju Kim , Hae-Rang Choi
发明人： Jae-Min JANG , Yong-Ju Kim , Hae-Rang Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0816 , H03L7/095 , H03L2207/14
摘要： A delay locked loop includes a delay unit delaying an input clock to generate an output clock, a replica delay unit delaying the output clock to generate a feedback clock, a phase comparing unit outputting a phase signal having a first or second value according to whether the phase of the feedback clock leads the phase of the input clock, a filtering unit generates a filtering signal in response to the phase signal and updates the filtering signal when a difference of count numbers of the phase signal having the first value and the second value is substantially equal to a filtering depth, a locking unit generates a locking signal in response to the filtering signal, and a control unit adjusts a delay value in response to the filtering signal and maintains the delay value when the locking signal is activated.
摘要翻译：延迟锁定环包括延迟单元延迟输入时钟以产生输出时钟，复制延迟单元延迟输出时钟以产生反馈时钟;相位比较单元，根据是否输出第一或第二值输出具有第一或第二值的相位信号反馈时钟的相位导致输入时钟的相位，滤波单元响应于相位信号产生滤波信号，并且当具有第一值和第二值的相位信号的计数数的差为基本上等于滤波深度，锁定单元响应于滤波信号产生锁定信号，并且控制单元响应于滤波信号调整延迟值，并且当锁定信号被激活时维持延迟值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式