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    • 32. 发明申请
    • METHOD OF MANUFACTURING AN ARRAY SUBSTRATE FOR LCD DEVICE HAVING DOUBLE-LAYERED METAL STRUCTURE
    • 具有双层金属结构的液晶显示装置制造阵列基板的方法
    • US20100203687A1
    • 2010-08-12
    • US12761174
    • 2010-04-15
    • Won-Ho CHOGyoo-Chul JoGue-Tai LeeJin-Gyu KangBeung-Hwa JeongJin-Young Kim
    • Won-Ho CHOGyoo-Chul JoGue-Tai LeeJin-Gyu KangBeung-Hwa JeongJin-Young Kim
    • H01L21/86
    • G02F1/136286G02F2001/13629G02F2001/136295
    • The present invention is an array substrate for use in a liquid crystal display device, which includes a gate electrode, a gate line and a gate pad on a substrate, wherein the gate electrode, the gate line and the gate pad have a double-layered structure consisting of a first metal layer and a first barrier metal layer in series from the substrate, and wherein the first metal is one of aluminum and aluminum alloy; a gate insulation layer on the substrate covering the gate electrode, gate line and gate pad; an active layer and an ohmic contact layer sequentially formed on the gate insulation layer and over the gate electrode; a data line on the gate insulation layer perpendicularly crossing the gate line, source and drain electrodes contacting the ohmic contact layer, and a data pad on the gate insulation layer, wherein the data line, the source and drain electrode and the data pad have a double-layered structure consisting of a second barrier metal layer and a second metal layer of copper; a passivation layer formed on the gate insulation layer to cover the data line, source and drain electrodes, and data pad, wherein the passivation layer has a drain contact hole exposing a portion of the drain electrode, a gate pad contact hole exposing a portion of the gate pad, and a data pad contact hole exposing a portion of the data pad; and a pixel electrode, a gate pad terminal and a data pad terminal on the passivation layer, all of which are formed of a transparent conductive material on the passivation layer.
    • 本发明是一种用于液晶显示装置的阵列基板,其包括在基板上的栅电极,栅极线和栅极焊盘,其中栅电极,栅极线和栅极焊盘具有双层 结构由第一金属层和与基板串联的第一阻挡金属层组成,其中第一金属是铝和铝合金之一; 覆盖栅电极,栅极线和栅极焊盘的基板上的栅极绝缘层; 依次形成在栅极绝缘层上和栅电极上的有源层和欧姆接触层; 垂直于栅极线的栅极绝缘层上的数据线,与欧姆接触层接触的源极和漏极以及栅极绝缘层上的数据焊盘,其中,数据线,源极和漏极以及数据焊盘具有 由第二阻挡金属层和铜的第二金属层组成的双层结构; 形成在所述栅极绝缘层上以覆盖所述数据线,源极和漏极以及数据焊盘的钝化层,其中所述钝化层具有暴露所述漏电极的一部分的漏极接触孔, 栅极焊盘和暴露数据焊盘的一部分的数据焊盘接触孔; 以及钝化层上的像素电极,栅极焊盘端子和数据焊盘端子,所有这些都由钝化层上的透明导电材料形成。
    • 36. 发明授权
    • Semiconductor integrated circuit and method of operating the same
    • 半导体集成电路及其操作方法
    • US07701793B2
    • 2010-04-20
    • US11882931
    • 2007-08-07
    • Jin-Young KimKi-Whan SongDuk-Ha Park
    • Jin-Young KimKi-Whan SongDuk-Ha Park
    • G11C7/00
    • G11C11/4091G11C11/4096G11C2207/002G11C2207/005G11C2211/4016
    • One embodiment includes a plurality of word lines, a plurality of bit lines intersecting with the plurality of word lines, a plurality of memory cells formed at intersections of and connected to the plurality of word lines and the plurality of bit lines. Each of the plurality of memory cells may be a floating body cell. A bit line selecting circuit may be configured to selectively connect each of the plurality of bit lines to an output bit line. The embodiment may further include plurality of sense amplifiers, where the plurality of sense amplifiers is greater than one and less than the plurality of bit lines in number. A sense amplifier switching structure may be configured to selectively connect each of the plurality of sense amplifiers to the output bit line.
    • 一个实施例包括多个字线,与多个字线相交的多个位线,多个存储单元,形成在多个字线和多个位线的交叉点处并与之连接。 多个存储单元中的每一个可以是浮动体单元。 位线选择电路可以被配置为选择性地将多个位线中的每一个连接到输出位线。 该实施例还可以包括多个读出放大器,其中多个读出放大器的数量大于一个且小于多个位线。 读出放大器切换结构可以被配置为选择性地将多个读出放大器中的每一个连接到输出位线。
    • 38. 发明申请
    • Driver circuit having high reliability and performance and semiconductor memory device including the same
    • 具有高可靠性和性能的驱动电路和包括该驱动电路的半导体存储器件
    • US20090302897A1
    • 2009-12-10
    • US12457240
    • 2009-06-04
    • Jin-Young KimKi-Whan Song
    • Jin-Young KimKi-Whan Song
    • H03K3/00
    • H03K19/018521G11C8/08G11C11/4085
    • Example embodiments relate to a driver circuit and a semiconductor memory device including the driver circuit. The driver circuit includes a pull-up unit configured to connect an output node to a first power supply voltage in response to an input signal, an interface unit connected between the output node and a first node to decrease a voltage of the output node in response to a control signal, and a pull-down unit configured to connect the first node to a second power supply voltage. The interface unit includes a first transistor configured to connect the output node with the first node in response to the control signal and a first resistor connected between the output node and the first node. The interface unit may also include a second resistor and a second transistor connected in series between the output node and the first node.
    • 示例实施例涉及包括驱动器电路的驱动器电路和半导体存储器件。 驱动器电路包括上拉单元,其被配置为响应于输入信号将输出节点连接到第一电源电压,连接在输出节点和第一节点之间的接口单元,以响应地降低输出节点的电压 以及被配置为将第一节点连接到第二电源电压的下拉单元。 接口单元包括第一晶体管,其被配置为响应于控制信号将输出节点与第一节点连接,以及连接在输出节点和第一节点之间的第一电阻器。 接口单元还可以包括串联连接在输出节点和第一节点之间的第二电阻器和第二晶体管。