专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07812754B2 Digital to analog converter and method thereof 有权
标题翻译：数模转换器及其方法
公开(公告)号：US07812754B2
公开(公告)日：2010-10-12
申请号：US12338633
申请日：2008-12-18
申请人： Jer-Hau Hsu , Tien-Yen Wang , Hsin-Yi Ho
发明人： Jer-Hau Hsu , Tien-Yen Wang , Hsin-Yi Ho
IPC分类号： H03M1/78
CPC分类号： H03M1/808
摘要： A digital to analog converter (DAC) has a plurality of transistor-resistor units connected in a string. Each of the transistor-resistor units of the DAC has a pair of transistors that are turned on/off by a pair of complementary control signals. Since the two transistors of each transistor-resistor unit are positioned symmetrically, an equivalent resistance would be determined precisely according to received digital codes, such that an output voltage of the DAC could be adjusted precisely based on the equivalent resistance.
摘要翻译：数模转换器（DAC）具有串联连接的多个晶体管电阻单元。 DAC的每个晶体管 - 电阻单元都有一对晶体管，通过一对互补控制信号导通/截止。由于每个晶体管 - 电阻器单元的两个晶体管对称地定位，所以根据接收到的数字代码精确地确定等效电阻，使得可以基于等效电阻精确地调整DAC的输出电压。

32. 发明申请

US20100027331A1 MEMORY AND READING METHOD THEREOF 有权
标题翻译：存储器及其读取方法
公开(公告)号：US20100027331A1
公开(公告)日：2010-02-04
申请号：US12183285
申请日：2008-07-31
申请人： Chun-Hsiung HUNG , Hsin-Yi HO
发明人： Chun-Hsiung HUNG , Hsin-Yi HO
IPC分类号： G11C16/26
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/26 , G11C2211/5612
摘要： A method for reading a memory, which includes a memory cell having a first half cell and a second half cell, includes the following steps. A first voltage is applied to the memory cell to determine whether a threshold voltage of the first half cell is higher than a predetermined value or not. If the threshold voltage of the first half cell is higher than the predetermined value, a second voltage higher than the first voltage is applied to the memory cell to read data stored in the second half cell, otherwise a third voltage lower than the first voltage is applied to the memory cell to read the data stored in the second half cell.
摘要翻译：一种用于读取存储器的方法，其包括具有第一半单元和第二半单元的存储单元，包括以下步骤。向存储单元施加第一电压，以确定第一半单元的阈值电压是否高于预定值。如果第一半单元的阈值电压高于预定值，则向存储单元施加高于第一电压的第二电压以读取存储在第二半单元中的数据，否则低于第一电压的第三电压为应用于存储器单元以读取存储在第二半单元中的数据。

33. 发明申请

US20100002505A1 READING METHOD FOR MLC MEMORY AND READING CIRCUIT USING THE SAME 有权
标题翻译：用于MLC存储器和读取电路的读取方法
公开(公告)号：US20100002505A1
公开(公告)日：2010-01-07
申请号：US12167265
申请日：2008-07-03
申请人： Hsin-Yi Ho , Ji-Yu Hung
发明人： Hsin-Yi Ho , Ji-Yu Hung
IPC分类号： G11C16/06
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/3418 , G11C16/3427
摘要： A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages.
摘要翻译：多级单元（MLC）存储器的读取方法包括以下步骤。多个字线电压被顺序提供给MLC存储单元。对应于字线电压的多个位线电压被依次提供给MLC存储单元。字线电压之一高于另一个字线电压，并且与字线电压中的一个相对应的位线电压之一低于对应于另一个字线电压的另一个位线电压字线电压。

34. 发明申请

US20090021994A1 MEMORY AND METHOD FOR PROGRAMMING THE SAME 有权
标题翻译：用于编程其的存储器和方法
公开(公告)号：US20090021994A1
公开(公告)日：2009-01-22
申请号：US11779951
申请日：2007-07-19
申请人： Chun-Hsiung Hung , Hsin-Yi Ho , Wen-Chiao Ho
发明人： Chun-Hsiung Hung , Hsin-Yi Ho , Wen-Chiao Ho
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0475
摘要： A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data.
摘要翻译：一种用于编程存储器的方法，包括多个具有左半单元和右半单元的多级单元，包括以下步骤。首先，提供与要存储的2n组数据对应的目标地址，其中n是正整数。接下来，基于编程循环中的目标地址，将2n组数据顺序地编程到多电平单元中，使得存储在左半单元中的数据和存储在右半单元中的数据来自不同的组 2n组数据。

35. 发明授权

US07474565B2 Programming scheme for non-volatile flash memory 有权
标题翻译：非易失性闪存的编程方案
公开(公告)号：US07474565B2
公开(公告)日：2009-01-06
申请号：US11636920
申请日：2006-12-11
申请人： Chun-Jen Huang , Chia-Jung Chen , Hsin-Yi Ho
发明人： Chun-Jen Huang , Chia-Jung Chen , Hsin-Yi Ho
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C2211/5621
摘要： An embodiment of the present invention involves a method of programming a memory cell. The memory cell is in a first state having a maximum initial threshold voltage. The memory cell is to be programmed to one of a plurality of states having a higher target threshold voltage relative to the maximum initial threshold voltage. There is a cue voltage between the maximum initial threshold voltage and the target threshold voltage. The memory cell has a drain region. The method includes applying a drain voltage to the cell by a programming pulse having a first width, determining whether the cell has reached the cue threshold voltage, and if the cell has reached the cue threshold voltage, changing the programming pulse width from the first pulse width to a second pulse width. The second pulse width is smaller than the first pulse width.
摘要翻译：本发明的一个实施例涉及一种编程存储器单元的方法。存储单元处于具有最大初始阈值电压的第一状态。存储器单元将被编程为具有相对于最大初始阈值电压的较高目标阈值电压的多个状态之一。在最大初始阈值电压和目标阈值电压之间存在一个提示电压。存储单元具有漏极区域。该方法包括通过具有第一宽度的编程脉冲向单元施加漏极电压，确定单元是否已经达到提示阈值电压，以及如果单元已经达到提示阈值电压，则从第一脉冲改变编程脉冲宽度宽度到第二个脉冲宽度。第二脉冲宽度小于第一脉冲宽度。

36. 发明授权

US08738844B2 Program method, data recovery method, and flash memory using the same 有权
标题翻译：程序方法，数据恢复方法和闪存使用相同
公开(公告)号：US08738844B2
公开(公告)日：2014-05-27
申请号：US13086988
申请日：2011-04-14
申请人： Lung-Yi Kuo , Hsin-Yi Ho , Chun-Hsiung Hung , Shuo-Nan Hung , Han-Sung Chen
发明人： Lung-Yi Kuo , Hsin-Yi Ho , Chun-Hsiung Hung , Shuo-Nan Hung , Han-Sung Chen
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/02 , G11C16/10 , G06F11/00
CPC分类号： G06F12/0246 , G06F11/00 , G06F2212/7201 , G06F2212/7203 , G11C16/10 , G11C16/105 , G11C2211/5648
摘要： A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.
摘要翻译：提供了一种用于多级单元（MLC）闪速存储器的程序方法。存储器阵列包括对应于各个页面的多个页面和多个配对页面。程序方法包括以下步骤。首先，获得程序地址命令。接下来，确定与配对页中的任何一个对应的程序地址命令。当程序地址命令对应于对应于页面中的第一页的第一配对页面时，在配对页面中，复制存储在第一页面中的非易失性存储器的数据。之后，第一个配对的页面被编程。

37. 发明申请

US20120011300A1 METHOD AND APPARATUS FOR HIGH-SPEED BYTE-ACCESS IN BLOCK-BASED FLASH MEMORY 有权
标题翻译：用于基于块式闪存的高速字节访问的方法和装置
公开(公告)号：US20120011300A1
公开(公告)日：2012-01-12
申请号：US12833305
申请日：2010-07-09
申请人： CHUN-HSIUNG HUNG , Hsin-Yi Ho , Hsiang-Pang Li
发明人： CHUN-HSIUNG HUNG , Hsin-Yi Ho , Hsiang-Pang Li
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： Techniques utilizing an erase-once, program-many progressive indexing structure manage data in a flash memory device which avoids the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. Consequently, block-based flash memory can be used for high-speed byte access.
摘要翻译：利用一次擦除一次程序的渐进式索引结构的技术管理闪速存储器件中的数据，这避免了每次更新存储在闪速存储器件中的数据时执行扇区擦除操作。结果，在需要扇区擦除操作之前可以执行大量写入操作。因此，基于块的闪存可用于高速字节访问。

38. 发明授权

US08094494B2 Memory and operation method therefor 有权
标题翻译：记忆和操作方法
公开(公告)号：US08094494B2
公开(公告)日：2012-01-10
申请号：US12576323
申请日：2009-10-09
申请人： Hsin-Yi Ho , Chun-Hsiung Hung , Yun-Chen Chou
发明人： Hsin-Yi Ho , Chun-Hsiung Hung , Yun-Chen Chou
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/26 , G11C16/349
摘要： In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on the memory cells by applying the moved reference voltage; a first total number of a first logic state in the first reading is compared with a second total number of the first logic state in the second reading if it is checked that the second reading result is not correct; and the moving of the reference voltage is stopped if the first reading result has the same number of the first logic state as the second reading result, and the moved reference voltage is stored as a target reference voltage.
摘要翻译：在包括多个存储单元的存储器的操作方法中，通过施加参考电压对存储器单元执行第一读取; 如果检查到第一读取结果不正确，则移动参考电压; 通过施加移动的参考电压对存储器单元执行第二读取; 如果检查到第二读取结果不正确，则将第一读取中的第一逻辑状态的第一总数与第二读取中的第一逻辑状态的第二总数进行比较; 并且如果第一读取结果具有与第二读取结果相同数量的第一逻辑状态，并且移动的参考电压被存储为目标参考电压，则参考电压的移动停止。

39. 发明授权

US08077513B2 Method and apparatus for programming a multi-level memory 有权
标题翻译：用于编程多级存储器的方法和装置
公开(公告)号：US08077513B2
公开(公告)日：2011-12-13
申请号：US12566144
申请日：2009-09-24
申请人： Hsin-Yi Ho , Chia-Ching Li , Chun-Hsiung Hung
发明人： Hsin-Yi Ho , Chia-Ching Li , Chun-Hsiung Hung
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/3436
摘要： A method of programming a memory device comprising a plurality of memory cells may include verifying a first memory cell targeted to a first level with a first preliminary voltage of a first program phase (PPV1′), programming the first memory cell targeted to the first level in the first program phase, and verifying the first memory cell with a first post program-verify voltage of the first program phase (PV1′) in which the first post program-verify voltage is different from the first preliminary voltage. A corresponding apparatus is also provided.
摘要翻译：编程包括多个存储器单元的存储器件的方法可以包括使用第一编程相位（PPV1'）的第一初级电压来验证目标为第一电平的第一存储器单元，编程针对第一级的第一存储器单元在第一编程阶段中，并且以第一编程后验证电压与第一初步电压不同的第一编程相位（PV1'）的第一后编程验证电压来验证第一存储单元。还提供了相应的装置。

40. 发明申请

US20110292728A1 INTEGRATED CIRCUIT OF DEVICE FOR MEMORY CELL 有权
标题翻译：用于存储器的器件的集成电路
公开(公告)号：US20110292728A1
公开(公告)日：2011-12-01
申请号：US13209241
申请日：2011-08-12
申请人： Hsin-Yi Ho , Ji-Yu Hung
发明人： Hsin-Yi Ho , Ji-Yu Hung
IPC分类号： G11C16/10 , G11C16/26
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/3418 , G11C16/3427
摘要： A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages.
摘要翻译：多级单元（MLC）存储器的读取方法包括以下步骤。多个字线电压被顺序提供给MLC存储单元。对应于字线电压的多个位线电压被依次提供给MLC存储单元。字线电压之一高于另一个字线电压，并且与字线电压中的一个相对应的位线电压之一低于对应于另一个字线电压的另一个位线电压字线电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式