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31. 发明授权

US08278981B2 Low power variable delay circuit 有权
标题翻译：低功率可变延迟电路
公开(公告)号：US08278981B2
公开(公告)日：2012-10-02
申请号：US12636901
申请日：2009-12-14
申请人： Hae-Rang Choi , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hae-Rang Choi , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03L7/00
CPC分类号： G11C19/28
摘要： A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.
摘要翻译：可变延迟电路至少包括固定延迟单元，第一选择单元和可变延迟单元。固定延迟单元接收表示第一延迟的输入信号和第一延迟选择信号，并且输出基本上延迟了第一延迟的输入信号的第一延迟信号。第一选择单元接收输入信号，第一延迟信号和第二延迟选择信号，并且基于第二延迟选择信号将输入信号或第一延迟信号输出到可变延迟单元。可变延迟单元还接收表示第三延迟的第三延迟选择信号，并且输出基本上延迟了第三延迟的选择单元的输出信号的输出信号。第一个延迟是M个延迟单位的0或X倍。第三延迟是从0到N个延迟单元中选择的延迟。

32. 发明授权

US08139703B2 Data relay apparatus and semiconductor integrated circuit having the same 失效
标题翻译：数据中继装置及具有该数据中继装置的半导体集成电路
公开(公告)号：US08139703B2
公开(公告)日：2012-03-20
申请号：US12038616
申请日：2008-02-27
申请人： Ic-Su Oh , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
发明人： Ic-Su Oh , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： H03D3/24
CPC分类号： H03K5/135 , H03L7/06
摘要： A data relay apparatus according to one embodiment described herein can include a phase detection unit that can detect a phase difference between a clock output from a transmitter and a clock output from a receiver, and generate a plurality of phase detection signals, a data relay control unit that can distinguish a difference in clock timing between the clocks of the transmitter and the receiver in response to the plurality of phase detection signals, and output a relay data selection signal and a relay control clock, and a data relay unit that can transmit data output from the receiver to the transmitter in response to the relay data selection signal and the relay control clock.
摘要翻译：根据本文所述的一个实施例的数据中继装置可以包括相位检测单元，其可以检测从发送器输出的时钟与从接收器输出的时钟之间的相位差，并且生成多个相位检测信号，数据中继控制单元，其可以响应于所述多个相位检测信号来区分发射机和接收机的时钟之间的时钟定时的差异，并且输出中继数据选择信号和中继控制时钟，以及可以发送数据的数据中继单元响应于继电器数据选择信号和继电器控制时钟从接收器输出到发送器。

33. 发明申请

US20110267117A1 DATA INPUT/OUTPUT APPARATUS AND METHOD FOR SEMICONDUCTOR SYSTEM 有权
标题翻译：数据输入/输出设备和半导体系统的方法
公开(公告)号：US20110267117A1
公开(公告)日：2011-11-03
申请号：US12832312
申请日：2010-07-08
申请人： Hae-Rang CHOI , Yong-Ju Kim , Jae-Min Jang
发明人： Hae-Rang CHOI , Yong-Ju Kim , Jae-Min Jang
IPC分类号： H03L7/06 , H03L7/00
CPC分类号： H03L7/00
摘要： A semiconductor memory device includes: a strobe signal reception unit configured to receive a strobe signal and generate a tracking clock signal; a clock reception unit configured to receive a clock signal and generate an internal clock signal; a plurality of data reception units configured to receive parallel data in accordance with the internal clock signal and generate internal data; and a phase control unit configured to control the phase of the internal clock signal to track the tracking clock signal and to compensate for a variation in the phase of the internal clock signal while the data is received.
摘要翻译：半导体存储器件包括：选通信号接收单元，被配置为接收选通信号并产生跟踪时钟信号; 时钟接收单元，被配置为接收时钟信号并产生内部时钟信号; 多个数据接收单元，被配置为根据内部时钟信号接收并行数据并产生内部数据; 以及相位控制单元，被配置为控制内部时钟信号的相位以跟踪跟踪时钟信号，并且在接收数据时补偿内部时钟信号的相位的变化。

34. 发明授权

US07915939B2 Duty cycle correction apparatus and semiconductor integrated circuit having the same 有权
标题翻译：占空比校正装置和具有该占空比校正装置的半导体集成电路
公开(公告)号：US07915939B2
公开(公告)日：2011-03-29
申请号：US12407727
申请日：2009-03-19
申请人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
发明人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
IPC分类号： H03K5/04
CPC分类号： H03K5/1565 , H03K2005/00052 , H03L7/0814
摘要： A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal.
摘要翻译：占空比校正装置包括：固定延迟单元，被配置为将固定延迟时间设置为DLL时钟信号，并产生延迟上升时钟信号; 可变延迟单元，被配置为响应于控制信号延迟所述DLL时钟信号并产生延迟下降时钟信号; 占空比校正单元，被配置为产生与延迟上升时钟信号和延迟下降时钟信号的边沿定时一致的校正上升时钟信号和校正下降时钟信号; 以及延迟控制单元，被配置为检测所述校正上升时钟信号和所述校正下降时钟信号的占空比，并产生所述控制信号。

35. 发明授权

US07864605B2 Apparatus for removing crosstalk in semiconductor memory device 失效
标题翻译：用于去除半导体存储器件中的串扰的装置
公开(公告)号：US07864605B2
公开(公告)日：2011-01-04
申请号：US12347518
申请日：2008-12-31
申请人： Ji-Wang Lee , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi
发明人： Ji-Wang Lee , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C5/063 , G11C7/1078 , G11C7/1084
摘要： An apparatus for removing crosstalk in a semiconductor memory device includes pads for receiving externally provided signals, transmission lines for delivering the signals received by each of the pads to corresponding elements in the apparatus, and capacitors, coupled between adjacent ones of the lines, for adjusting the transmission delay of the signals depending on a signal transmission mode between the adjacent lines.
摘要翻译：一种用于去除半导体存储器件中的串扰的装置包括用于接收外部提供的信号的焊盘，用于将由每个焊盘接收的信号传递到设备中的相应元件的传输线以及耦合在相邻线之间的电容器，以便调整信号的传输延迟取决于相邻线路之间的信号传输模式。

36. 发明申请

US20100301912A1 DELAY LOCKED LOOP AND DELAY LOCKING METHOD HAVING BURST TRACKING SCHEME 有权
标题翻译：延迟锁定方式的延迟锁定和延迟锁定方法
公开(公告)号：US20100301912A1
公开(公告)日：2010-12-02
申请号：US12494509
申请日：2009-06-30
申请人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/093
摘要： A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock.
摘要翻译：延迟锁定环（DLL）包括复制延迟单元，其被配置为延迟输出时钟以产生反馈时钟; 相位检测器，被配置为测量反馈时钟和输入时钟之间的相位差; 量化单元，被配置为量化由相位检测器测量的相位差; 以及延迟单元，被配置为基于来自量化单元的量化结果来延迟输入时钟，以产生输出时钟。

37. 发明申请

US20100250994A1 DATA PATTERN DETECTING CIRCUIT AND OUTPUT DRIVER INCLUDING THE SAME 审中-公开
标题翻译：数据模式检测电路和输出驱动器，包括它们
公开(公告)号：US20100250994A1
公开(公告)日：2010-09-30
申请号：US12495332
申请日：2009-06-30
申请人： Chang-Kun Park , Yong-Ju Kim , Kyung-Whan Kim , Sung-Woo Han , Jae-Il Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang
发明人： Chang-Kun Park , Yong-Ju Kim , Kyung-Whan Kim , Sung-Woo Han , Jae-Il Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang
IPC分类号： G06F1/12
CPC分类号： G06F13/4077
摘要： Disclosed is an output driver capable of solving problems that occur when outputting the same data successively by using a data pattern detecting circuit. The data pattern detecting circuit includes a first data storage unit configured to receive data of a first line and store the received data until a next data is inputted through the first line, a second data storage unit configured to receive data of a second line and store the received data until a next data is inputted through the second line, and a detection signal output unit configured to activate a pattern detection signal when data stored in the first data storage unit and data stored in the second data storage unit have the same logic level.
摘要翻译：公开了一种能够解决通过使用数据模式检测电路连续输出相同数据时出现的问题的输出驱动器。数据模式检测电路包括：第一数据存储单元，被配置为接收第一行的数据并存储接收的数据，直到通过第一行输入下一个数据;第二数据存储单元，被配置为接收第二行的数据并存储所接收的数据直到通过第二行输入下一个数据;以及检测信号输出单元，被配置为当存储在第一数据存储单元中的数据和存储在第二数据存储单元中的数据具有相同的逻辑电平时激活模式检测信号。

38. 发明申请

US20100117696A1 DLL CIRCUIT, UPDATE CONTROL APPARATUS IN DLL CIRCUIT AND UPDATE METHOD OF DLL CIRCUIT 有权
标题翻译： DLL电路中的DLL电路，更新控制装置和DLL电路的更新方法
公开(公告)号：US20100117696A1
公开(公告)日：2010-05-13
申请号：US12493387
申请日：2009-06-29
申请人： Jae Min JANG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Hae Rang CHOI , Ji Wang LEE , Chang Kun PARK
发明人： Jae Min JANG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Hae Rang CHOI , Ji Wang LEE , Chang Kun PARK
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/085
摘要： A delay locked loop (DLL) circuit includes a phase detection unit configured to generate a phase detection signal by comparing a phase of a reference clock signal with a phase of a feedback clock signal. An update control apparatus is configured to generate a valid interval signal and an update control signal by determining a difference between the number of first logical values and the number of second logical values of the phase detection signal in response to the reference clock signal. A shift register configured to update a delay value granted to a delay line in response to the update control signal when the valid interval signal is enabled.
摘要翻译：延迟锁定环路（DLL）电路包括：相位检测单元，被配置为通过将参考时钟信号的相位与反馈时钟信号的相位进行比较来产生相位检测信号。更新控制装置被配置为通过响应于参考时钟信号确定第一逻辑值的数量和相位检测信号的第二逻辑值的数量之间的差异来产生有效间隔信号和更新控制信号。移位寄存器，被配置为当有效间隔信号被使能时响应于更新控制信号来更新授予延迟线的延迟值。

39. 发明申请

US20100060332A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20100060332A1
公开(公告)日：2010-03-11
申请号：US12340912
申请日：2008-12-22
申请人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03L7/06
CPC分类号： H03K3/0322 , H03K5/1504 , H03K2005/00208 , H03L7/083 , H03L7/24
摘要： A semiconductor integrated circuit comprises a PLL (Phase Locked Loop (PLL) circuit configured to generate a control voltage in response to a frequency of a reference clock signal, and to generate a PLL clock signal having a frequency that corresponds to a level of the control voltage, and a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal, and to allow the PLL clock signal to have a frequency that corresponds to a level of the control voltage.
摘要翻译：半导体集成电路包括PLL（锁相环）电路，其被配置为响应于参考时钟信号的频率产生控制电压，并且产生具有对应于控制电平的频率的PLL时钟信号电压和被配置为响应于PLL时钟信号而振荡输出时钟信号的压控振荡器，并且允许PLL时钟信号具有对应于控制电压电平的频率。

40. 发明申请

US20100044872A1 SEMICONDUCTOR MEMORY DEVICE HAVING PADS 有权
标题翻译：具有PADS的半导体存储器件
公开(公告)号：US20100044872A1
公开(公告)日：2010-02-25
申请号：US12493617
申请日：2009-06-29
申请人： Chang Kun PARK , Seong Hwi SONG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Hae Rang CHOI , Ji Wang LEE , Jae Min JANG
发明人： Chang Kun PARK , Seong Hwi SONG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Hae Rang CHOI , Ji Wang LEE , Jae Min JANG
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L24/06 , H01L23/5286 , H01L24/09 , H01L27/1052 , H01L2224/061 , H01L2224/0612 , H01L2224/06515 , H01L2224/091 , H01L2224/09515 , H01L2924/14 , H01L2924/1434 , H01L2924/30101 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
摘要翻译：半导体存储器件包括具有芯片焊盘形成区域的半导体电路基板。在芯片焊盘区域一侧的半导体电路基板上形成一对数据线。一对数据线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸。这对数据线被布置为彼此相邻并且接收一对差分数据信号。电源线形成在芯片焊盘区域的另一侧的半导体电路基板上。电源线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸，并且电源线接收电力。

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