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31. 发明授权

US6061794A System and method for performing secure device communications in a peer-to-peer bus architecture 失效
标题翻译：用于在对等总线架构中执行安全设备通信的系统和方法
公开(公告)号：US6061794A
公开(公告)日：2000-05-09
申请号：US940551
申请日：1997-09-30
申请人： Michael F. Angelo , Sompong P. Olarig , David R. Wooten , Dan J. Driscoll
发明人： Michael F. Angelo , Sompong P. Olarig , David R. Wooten , Dan J. Driscoll
IPC分类号： G06F1/00 , G06F21/00 , G06F12/14
CPC分类号： G06F21/6218 , G06F21/606 , G06F21/85 , G06F2211/007 , G06F2221/2141
摘要： A system and method for performing secure peer-to-peer device communications on an I/O bus, such as a PCI bus, a Fiber Channel bus, an IEEE, 1394 bus or a Universal Serial Bus. The system includes a plurality of intelligent I/O devices, such as intelligent storage devices and/or controllers, communications devices, video devices and audio devices. The I/O devices perform peer-to-peer message and data transfers, thereby bypassing the operating system running on the computer's CPU. The intelligent I/O devices encrypt messages and data before transmitting them on the I/O bus and conversely decrypt the messages and data upon reception. The encryption provides secrecy and/or authentication of the sender. The devices use keys or passwords to encrypt/decrypt the data. The keys are stored in non-volatile memory in the devices and are distributed to the devices by the system BIOS at initialization time. The devices perform access authorization validation using rule sets also distributed by the BIOS at initialization time. The rule sets specify which I/O operations are valid for a peer I/O device to request of a respective I/O device based, preferably, upon the device class/subclasses of the requesting device. In another embodiment, one of the intelligent I/O devices may be a communications device which serves as a firewall for the I/O bus. In this embodiment, the rule set further includes identification information of the remote machines/devices.
摘要翻译：用于在诸如PCI总线，光纤通道总线，IEEE，1394总线或通用串行总线的I / O总线上执行安全的对等设备通信的系统和方法。该系统包括多个智能I / O设备，诸如智能存储设备和/或控制器，通信设备，视频设备和音频设备。 I / O设备执行对等消息和数据传输，从而绕过计算机CPU上运行的操作系统。智能I / O设备在I / O总线上传输消息和数据之前加密消息和数据，并在接收时反向解密消息和数据。加密提供发送者的保密和/或认证。设备使用密钥或密码来加密/解密数据。密钥存储在设备的非易失性存储器中，并在初始化时由系统BIOS分发给设备。这些设备使用在BIOS初始化时分配的规则集执行访问授权验证。规则集指定哪个I / O操作对于对等I / O设备有效，以优选地基于请求设备的设备类/子类来请求相应的I / O设备。在另一个实施例中，智能I / O设备中的一个可以是用作I / O总线的防火墙的通信设备。在该实施例中，规则集还包括远程机器/设备的识别信息。

32. 发明授权

US6061687A Linked lists of transfer descriptors scheduled at intervals 有权
标题翻译：传输描述符的链接列表以间隔安排
公开(公告)号：US6061687A
公开(公告)日：2000-05-09
申请号：US158812
申请日：1998-09-22
申请人： David R. Wooten
发明人： David R. Wooten
IPC分类号： G06F13/10 , G06F13/26 , G06F17/00
CPC分类号： G06F13/102 , G06F13/26 , Y10S707/99942 , Y10S707/99943
摘要： A computer system including a serial bus host controller and host controller driver. The host controller driver providing data structures for the host controller to operate on. The data structures having a linking mechanism for processing lists of descriptors, and alternate buffer configurations for receiving data from the serial bus devices.
摘要翻译：一种包括串行总线主机控制器和主机控制器驱动程序的计算机系统。主机控制器驱动程序提供主机控制器操作的数据结构。具有用于处理描述符列表的链接机制的数据结构以及用于从串行总线设备接收数据的备用缓冲器配置。

33. 发明授权

US6061411A Method and apparatus for synchronizing a serial bus clock to a serial bus function clock 失效
标题翻译：将串行总线时钟同步到串行总线功能时钟的方法和装置
公开(公告)号：US6061411A
公开(公告)日：2000-05-09
申请号：US577625
申请日：1995-12-22
申请人： David R. Wooten
发明人： David R. Wooten
IPC分类号： H04L7/00 , H04L25/40 , H04L25/36
CPC分类号： H04J3/0632
摘要： A method and apparatus of synchronizing a serial bus data rate to a serial bus function data rate to eliminate the build up of overruns or underruns of data. A response is provided to a start of frame packet. The response packet contains a response code for indicating a modification to the serial bus frame counter. Thereby, slight variations in data rates can be eliminated by adjusting the serial bus data rate instead of the serial bus function data rate.
摘要翻译：一种将串行总线数据速率同步到串行总线功能数据速率的方法和装置，以消除数据超载或欠载的累积。对帧分组的开始提供响应。响应分组包含用于指示对串行总线帧计数器的修改的响应代码。因此，可以通过调整串行总线数据速率而不是串行总线功能数据速率来消除数据速率的微小变化。

34. 发明授权

US5621898A Arbiter organization for serial bus transfers 失效
标题翻译：仲裁组织串行总线传输
公开(公告)号：US5621898A
公开(公告)日：1997-04-15
申请号：US346097
申请日：1994-11-29
申请人： David R. Wooten
发明人： David R. Wooten
IPC分类号： G06F13/366 , G06F13/00 , G06F13/362 , H04L12/28 , G06F13/14 , H04L12/56
CPC分类号： G06F13/362
摘要： A serial bus host controller arbiter which organizes data transfer events into three categories, periodic data transfers, which are usually isochronous transfers; aperiodic transfers, which usually are asynchronous transfers; and control transfers. The arbiter fundamentally operates on a periodic basis. At the beginning of each period, the arbiter preferably alternates between periodic transfers and control transfers. When all of the periodic transfers have been completed, the arbiter then provides access to the various asynchronous transfers which are scheduled to occur, alternating with any remaining control transfers. The arbiter gives preference to the periodic events, and if any time within the period is available, which is referred to as the free time, control events are interleaved with periodic events until no free time remains or all are completed. Any remaining time in the period is used cycling through the aperiodic transfers. The arbiter of the preferred embodiment keeps a running total of free time during each period to determine if additional control or aperiodic transfers can occur.
摘要翻译：串行总线主机控制器仲裁器，将数据传输事件组织成三类，定时数据传输，通常是同步传输; 非周期性转移，通常是异步传输; 和控制转移。仲裁员从根本上定期运作。在每个时期的开始，仲裁者最好在周期性转移和控制转移之间进行交替。当所有周期性传输已经完成时，仲裁器然后提供对被调度发生的各种异步传输的访问，与任何剩余的控制传输交替。仲裁者优先考虑周期性事件，并且如果在该周期内的任何时间可用（称为空闲时间），则控制事件与周期性事件交错，直到没有空闲时间或全部完成为止。该期间的任何剩余时间都是通过非周期性转移使用。优选实施例的仲裁器在每个周期期间保持运行总共空闲时间以确定是否可以发生额外的控制或非周期性传送。

35. 发明授权

US4389715A Redundancy scheme for a dynamic RAM 失效
标题翻译：动态RAM的冗余方案
公开(公告)号：US4389715A
公开(公告)日：1983-06-21
申请号：US194613
申请日：1980-10-06
申请人： Sargent S. Eaton, Jr. , David R. Wooten
发明人： Sargent S. Eaton, Jr. , David R. Wooten
IPC分类号： G11C29/00 , G11C29/04 , G11C11/40
CPC分类号： G11C29/808
摘要： A redundancy scheme is described for replacing defective main memory cells in a dynamic RAM with spare memory cells. The spare cells are arranged in groups of spare rows and spare columns of memory cells such that a plurality of groups of spare rows and columns of cells are substituted for defective main rows and columns of cells so as to repair relatively large defects which impair adjacent rows and columns of main memory cells. In the preferred embodiment, the RAM includes a plurality of address buffers, each of which receives an incoming row address bit and then an incoming column address bit for sequentially outputting row and column address data. Associated with each buffer is a store for a defective row address, a store for a defective column address, and a comparator. The stores retain defective memory cell addresses which the comparator sequentially compares against the address data sequentially output by the buffer. When the comparator senses a match, a control signal is generated to initiate substitution of spare memory cells for the defective main memory cells.
摘要翻译：描述了用于用备用存储器单元替换动态RAM中的有缺陷的主存储器单元的冗余方案。备用单元被布置成存储器单元的备用行和备用列的组，使得多组备用行和单元列被替换有缺陷的主行和单元列，以便修复相对较大的相邻行的缺陷和主存储单元的列。在优选实施例中，RAM包括多个地址缓冲器，每个地址缓冲器接收输入行地址位，然后接收输入列地址位，用于顺序地输出行和列地址数据。与每个缓冲器相关联的是存储缺陷行地址，存储有缺陷列地址和比较器的存储。存储器保持缺陷的存储单元地址，比较器顺序地与由缓冲器顺序输出的地址数据进行比较。当比较器感测到匹配时，产生控制信号以启动用于缺陷主存储器单元的备用存储器单元的替换。

36. 发明授权

US10172305B2 Diagnostic molecular markers for seed lot purity traits in soybeans 有权
公开(公告)号：US10172305B2
公开(公告)日：2019-01-08
申请号：US14114642
申请日：2012-04-26
申请人： Jennifer Yates , Holly Kleiss , John P. Tamulonis , David R. Wooten, Jr. , Kunsheng Wu
发明人： Jennifer Yates , Holly Kleiss , John P. Tamulonis , David R. Wooten, Jr. , Kunsheng Wu
IPC分类号： A01H1/04 , A01H5/10 , C07K14/415 , C12N9/02
摘要： The present invention is in the field of plant breeding. More specifically, the invention includes a method for breeding and selecting plants that uniform for one or more seed lot purity traits such as, such as distinct flower color, pubescence color, hilum color, and pod wall color. The invention further includes molecular markers associated with distinct flower color, pubescence color, hilum color, and pod wall color for uses in a breeding program.

37. 发明申请

US20140115732A1 Diagnostic Molecular Markers for Seed Lot Purity Traits in Soybeans 审中-公开
标题翻译：大豆种子纯度性状的诊断分子标记
公开(公告)号：US20140115732A1
公开(公告)日：2014-04-24
申请号：US14114642
申请日：2012-04-26
申请人： Jennifer Yates , Holly Kleiss , John P. Tamulonis , David R. Wooten, JR. , Kunsheng Wu
发明人： Jennifer Yates , Holly Kleiss , John P. Tamulonis , David R. Wooten, JR. , Kunsheng Wu
IPC分类号： A01H1/04
CPC分类号： A01H1/04 , A01H5/10 , C07K14/415 , C12N9/0073 , C12Y114/13088
摘要： The present invention is in the field of plant breeding. More specifically, the invention includes a method for breeding and selecting plants that uniform for one or more seed lot purity traits such as, such as distinct flower color, pubescence color, hilum color, and pod wall color. The invention further includes molecular markers associated with distinct flower color, pubescence color, hilum color, and pod wall color for uses in a breeding program.
摘要翻译：本发明在植物育种领域。更具体地，本发明包括用于育种和选择对于一种或多种种子纯度性状均匀的植物的方法，例如不同的花色，柔毛色，门窗颜色和荚果壁颜色。本发明还包括与繁殖程序中使用的不同花色，柔毛色，门窗颜色和荚果壁颜色相关联的分子标记。

38. 发明授权

US07917723B2 Address translation table synchronization 有权
标题翻译：地址转换表同步
公开(公告)号：US07917723B2
公开(公告)日：2011-03-29
申请号：US11291726
申请日：2005-12-01
申请人： David R. Wooten
发明人： David R. Wooten
IPC分类号： G06F12/00
CPC分类号： G06F12/1027
摘要： A system, method and computer-readable medium for updating an address translation table. In the method, a message indicating a physical memory location that corresponds to a virtual address is received from a processor. An I/O Memory Management Unit (IOMMU) is used to update an entry within the address translation table corresponding to the virtual address according to the indicated physical memory location.
摘要翻译：一种用于更新地址转换表的系统，方法和计算机可读介质。在该方法中，从处理器接收指示对应于虚拟地址的物理存储器位置的消息。 I / O存储器管理单元（IOMMU）用于根据指示的物理存储器位置更新对应于虚拟地址的地址转换表中的条目。

39. 发明授权

US07499057B2 Address translation in an integrated graphics environment 有权
标题翻译：在集成图形环境中进行地址转换
公开(公告)号：US07499057B2
公开(公告)日：2009-03-03
申请号：US11222551
申请日：2005-09-09
申请人： David R. Wooten
发明人： David R. Wooten
IPC分类号： G06F12/10 , G06F9/26
CPC分类号： G06F12/1009
摘要： A method of translating graphics virtual addresses to physical addresses in an integrated graphics processor environment includes receiving a request for a graphics operation from an application. The application may be an application executing in a partition of a virtual machine. The requested graphics operation involves at least one instruction and at least one graphics virtual address. The instructions are accessed and execution begins by instruction execution within a graphics processor. The graphics processor relies upon an I/O memory management unit to perform a virtual address to physical address translation as the graphics processor performs the graphics operation. The I/O memory management unit may utilize direct memory access to accomplish the graphics operation.
摘要翻译：将图形虚拟地址转换为集成图形处理器环境中的物理地址的方法包括从应用程序接收对图形操作的请求。应用程序可以是在虚拟机的分区中执行的应用程序。所请求的图形操作涉及至少一个指令和至少一个图形虚拟地址。指令被访问，并且执行由图形处理器内的指令执行开始。当图形处理器执行图形操作时，图形处理器依靠I / O存储器管理单元执行物理地址转换的虚拟地址。 I / O存储器管理单元可以利用直接存储器访问来完成图形操作。

40. 发明授权

US06542946B1 Dual mode differential transceiver for a universal serial bus 有权
标题翻译：用于通用串行总线的双模式差分收发器
公开(公告)号：US06542946B1
公开(公告)日：2003-04-01
申请号：US09493322
申请日：2000-01-28
申请人： David R. Wooten
发明人： David R. Wooten
IPC分类号： G06F1342
CPC分类号： G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： A computer system has a USB bus to which one or more USB-compatible devices can connect. One or more of the USB devices has an electrical interface that includes two transmitters and, if desired, a receiver for bidirectional data transmission. The transmitters preferably are dual output, differential transmitters. The transmitters include a slower transmitter and a faster transmitter. The faster transmitter can transmit data at a rate that is faster than the slower transmitter. The electrical interface also includes an electrical termination device that is disposed between the output terminals of the two transmitters. The termination device preferably comprises a pair of multi-purpose termination resistors that can provide serial termination or parallel termination depending whether the fast or slow transmitter is used. When transmitting using the slower transmitter, the receiving USB device disables all of its transmitters and the transmitting USB device disables the output of the faster transmitter by deasserting an output enable (OE) signal to the faster transmitter. The termination device provides serial termination and the data from the slower transmitter passes through the termination device. When transmitting using the faster transmitter, both receiving and transmitting USB devices assert single ended zero (SE0) signals to their slower transmitters which forces both of the slower transmitters' output signals to a low impedance state. In this latter transmission mode, the termination device provides parallel termination, effectively functioning as a “pull-down” terminator. With parallel termination, echoes effectively are reduced or eliminated and faster data rates are thereby attainable than are generally possible with serially-terminated transmission lines.
摘要翻译：计算机系统具有一个USB总线，一个或多个USB兼容设备可以连接到该总线。一个或多个USB设备具有电接口，其包括两个发射器，并且如果需要，包括用于双向数据传输的接收器。发射机最好是双输出差分发射机。发射机包括较慢的发射机和更快的发射机。更快的发射机可以以比较慢的发射机更快的速率传输数据。电接口还包括设置在两个发射器的输出端之间的电终端装置。终端设备优选地包括一对多用途终端电阻器，其可以根据是使用快速还是慢速发射机来提供串行终止或并行终端。当使用较慢的发射机进行传输时，接收的USB设备会禁用其所有发射机，并且发射的USB设备通过将更快的发射机的输出使能（OE）信号置低，来禁用较快发射机的输出。终端设备提供串行终端，来自较慢发射机的数据通过终端设备。当使用更快的发射机进行发射时，接收和发射USB设备都将其单端零（SE0）信号置于其较慢的发射机，这些发射机将较慢的发射机的输出信号强制为低阻抗状态。在后一种传输模式中，终端设备提供并行终端，有效地用作“下拉”终端器。通过并行终止，减少或消除回波，从而可以实现比串行端接的传输线通常可以实现更快的数据速率。

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