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31. 发明授权

US5576999A Redundancy circuit of a semiconductor memory device 失效
标题翻译：半导体存储器件的冗余电路
公开(公告)号：US5576999A
公开(公告)日：1996-11-19
申请号：US491348
申请日：1995-06-30
申请人： Jae-Chul Kim , Choong-Keun Kwak
发明人： Jae-Chul Kim , Choong-Keun Kwak
IPC分类号： G11C29/00 , G11C29/48 , G11C7/00
CPC分类号： G11C29/785 , G11C29/48
摘要： A redundancy circuit of the semiconductor memory device having a normal memory cell array for storing data, a redundant memory cell for repairing the fail cells in the normal memory, cell array, a normal decoder for receiving addresses and designating the normal memory cell, a redundancy decoder for selecting the redundant memory cell. The circuit includes a control part which is controlled by a control clock and has fuses for programming fail addresses of the addresses, to be applied, a transmission part which is controlled by an output signal of the control part and has a first path for outputting addresses in-phase with the addresses and a second path for outputting addresses out of phase with the addresses, thereby selecting the first path before repair to select both the normal memory cell and redundant memory cell by the normal and redundancy decoders, and cutting off the fuses corresponding to the fail addresses and selecting the second path during the repair to select the redundant memory cell by the redundancy decoder, thus enabling burn-in of both the normal memory cell and redundant memory cell during the burn-in test.
摘要翻译：具有用于存储数据的正常存储单元阵列的半导体存储器件的冗余电路，用于修复正常存储器中的故障单元的冗余存储单元，单元阵列，用于接收地址和指定正常存储单元的正常解码器，冗余用于选择冗余存储器单元的解码器。电路包括由控制时钟控制的控制部分，并且具有用于编程要应用的地址的失败地址的熔丝，由控制部分的输出信号控制的发送部分，并且具有用于输出地址的第一路径与地址同相，以及用于输出地址与地址异相的第二路径，从而在修复之前选择第一路径以通过正常和冗余解码器选择正常存储器单元和冗余存储器单元，并且切断熔丝对应于故障地址并且在修复期间选择第二路径以通过冗余解码器选择冗余存储器单元，从而在老化测试期间能够老化正常存储器单元和冗余存储器单元。

32. 发明授权

US5315173A Data buffer circuit with delay circuit to increase the length of a switching transition period during data signal inversion 失效
标题翻译：具有延迟电路的数据缓冲电路在数据信号反相期间增加开关转换周期的长度
公开(公告)号：US5315173A
公开(公告)日：1994-05-24
申请号：US898535
申请日：1992-06-15
申请人： Seung-keun Lee , Choong-keun Kwak , Chang-rae Kim
发明人： Seung-keun Lee , Choong-keun Kwak , Chang-rae Kim
IPC分类号： G11C11/417 , G11C7/02 , G11C11/409 , H01L27/10 , H03K17/16 , H03K19/003 , H03K19/0175 , H03K5/12 , H03K19/0948
CPC分类号： H03K19/00361
摘要： A data output buffer includes a data driving circuit having a pull-up transistor responsive to a first signal and a pull-down transistor responsive to a second signal, a first control circuit for regulating the slope of the first signal to be less steep after reaching the threshold of the pull-up transistor than before reaching the threshold of the pull-up transistor, and a second control circuit for regulating the slope of the second signal to be less steep after reaching the threshold of the pull-down transistor than before reaching the threshold of the pull-down transistor. As a result, noise generated by the transition of the output signal of the data output buffer is reduced without affecting operation speed.
摘要翻译：数据输出缓冲器包括数据驱动电路，其具有响应于第一信号的上拉晶体管和响应于第二信号的下拉晶体管;第一控制电路，用于在达到之后调节第一信号的斜率不太陡峭上拉晶体管的阈值比达到上拉晶体管的阈值之前的阈值为止;以及第二控制电路，用于在达到下拉晶体管的阈值之后将第二信号的斜率调整为不太陡峭下拉晶体管的阈值。结果，数据输出缓冲器的输出信号的转变产生的噪声减小而不影响操作速度。

33. 发明授权

US07994493B2 Phase change memory devices employing cell diodes and methods of fabricating the same 有权
标题翻译：使用单元二极管的相变存储器件及其制造方法
公开(公告)号：US07994493B2
公开(公告)日：2011-08-09
申请号：US12196137
申请日：2008-08-21
申请人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L29/04 , H01L47/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.
摘要翻译：相变存储器件可以包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线。字线可以具有不同于第一导电类型和基本上平坦的顶表面的第二导电类型。第一和第二半导体图案可以顺序地堆叠在每个字线上，并且可以提供绝缘层以填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体图案之间的间隙区域。多个相变材料图案可以二维排列在绝缘层上并电连接到第二半导体图案。

34. 发明申请

US20110053293A1 MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：磁记忆体装置及其制造方法
公开(公告)号：US20110053293A1
公开(公告)日：2011-03-03
申请号：US12915335
申请日：2010-10-29
申请人： Woo-Yeong CHO , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
发明人： Woo-Yeong CHO , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
IPC分类号： H01L21/62
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.
摘要翻译：磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体，写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

35. 发明授权

US07876609B2 Nonvolatile memory device and related methods of operation 有权
标题翻译：非易失存储器件及相关操作方法
公开(公告)号：US07876609B2
公开(公告)日：2011-01-25
申请号：US12720918
申请日：2010-03-10
申请人： Kwang-jin Lee , Choong-keun Kwak , Du-eung Kim
发明人： Kwang-jin Lee , Choong-keun Kwak , Du-eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0064
摘要： In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.
摘要翻译：在非易失性存储器件中，通过在第一程序间隔期间从多个非易失性存储单元中选出的多个选择的存储单元中的第一组中编程具有第一逻辑状态的数据，对多个非易失性存储单元执行编程操作并且此后，在所述第一编程间隔之后的所述程序操作的第二编程间隔期间，在所选择的存储单元之间具有与所述第二组中的第一逻辑状态不同的第二逻辑状态的编程数据。

36. 发明授权

US07710767B2 Memory cell array biasing method and a semiconductor memory device 有权
标题翻译：存储单元阵列偏置方法和半导体存储器件
公开(公告)号：US07710767B2
公开(公告)日：2010-05-04
申请号：US11969326
申请日：2008-01-04
申请人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译：一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件，其中半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多个第一行中的对应的第一行和存储单元的第二端连接到多条第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

37. 发明申请

US20090273045A1 MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：磁记忆体装置及其制造方法
公开(公告)号：US20090273045A1
公开(公告)日：2009-11-05
申请号：US12507504
申请日：2009-07-22
申请人： Woo-Yeong CHO , Yun-Seung SHIN , Hyun-Geun BYUN , Choong-Keun KWAK
发明人： Woo-Yeong CHO , Yun-Seung SHIN , Hyun-Geun BYUN , Choong-Keun KWAK
IPC分类号： H01L29/82 , G11C11/14
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.
摘要翻译：磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体，写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

38. 发明授权

US07499306B2 Phase-change memory device and method that maintains the resistance of a phase-change material in a set state within a constant resistance range 有权
标题翻译：相变存储器件和方法，其将相变材料的电阻保持在恒定电阻范围内的置位状态
公开(公告)号：US07499306B2
公开(公告)日：2009-03-03
申请号：US11772569
申请日：2007-07-02
申请人： Byung-gil Choi , Choong-keun Kwak , Sang-beom Kang , Joon-yong Choi
发明人： Byung-gil Choi , Choong-keun Kwak , Sang-beom Kang , Joon-yong Choi
IPC分类号： G11C11/00
CPC分类号： G11C7/1006 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5647
摘要： Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a set state within a constant resistance range. In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are not identical, a complementary write current is provided to the first phase-change memory cell and it is second determined whether the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical, data is provided to a second phase-change memory cell.
摘要翻译：提供一种将相变材料的电阻维持在恒定电阻范围内的置换状态的相变存储器件和方法。在该方法中，将数据提供给第一相变存储器单元，然后首先确定存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据是否相同。如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据不相同，则向第一相变存储单元提供互补写入电流，并且第二相位变换存储单元是否将数据存储在第一相变存储单元中，提供给第一相变存储单元的数据相同。如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据相同，则将数据提供给第二相变存储单元。

39. 发明授权

US07457151B2 Phase change random access memory (PRAM) device having variable drive voltages 有权
标题翻译：具有可变驱动电压的相变随机存取存储器（PRAM）装置
公开(公告)号：US07457151B2
公开(公告)日：2008-11-25
申请号：US11319601
申请日：2005-12-29
申请人： Woo-yeong Cho , Du-eung Kim , Sang-beom Kang , Choong-keun Kwak
发明人： Woo-yeong Cho , Du-eung Kim , Sang-beom Kang , Choong-keun Kwak
IPC分类号： G11C11/00
CPC分类号： G11C13/0038 , G11C5/145 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/009
摘要： A phase change memory device of one aspect includes a memory array including a plurality of phase change memory cells, a write boosting circuit, and a write driver. The write boosting circuit boosts a first voltage and outputs a first control voltage in response to a control signal in a first operation mode, and boosts the first voltage and outputs a second control voltage in response to the control signal in a second operation mode and a third operation mode. The write driver is driven by the first control voltage in the first operation mode and writes data to a selected memory cell of the memory array.
摘要翻译：一个方面的相变存储器件包括包括多个相变存储单元，写升压电路和写驱动器的存储器阵列。写升压电路响应于第一操作模式中的控制信号而升高第一电压并输出第一控制电压，并且在第二操作模式中响应于控制信号升高第一电压并输出第二控制电压，并且第三操作模式。写入驱动器由第一操作模式中的第一控制电压驱动，并将数据写入存储器阵列的所选存储单元。

40. 发明授权

US07391669B2 Semiconductor memory device and core layout thereof 失效
标题翻译：半导体存储器件及其核心布局
公开(公告)号：US07391669B2
公开(公告)日：2008-06-24
申请号：US11316878
申请日：2005-12-27
申请人： Hye-jin Kim , Choong-keun Kwak , Woo-yeong Cho , Sang-beom Kang
发明人： Hye-jin Kim , Choong-keun Kwak , Woo-yeong Cho , Sang-beom Kang
IPC分类号： G11C8/00
CPC分类号： G11C13/0028 , G11C13/0004
摘要： A semiconductor memory device of one aspect includes a memory cell block including n global word lines, and corresponding m sub word lines for each of the n global word lines, where n and m are natural numbers. The memory device further includes a plurality of word line driving circuits which respectively control a voltage of the sub word lines according to a logic level of each corresponding global word line and inputted address signals, and a plurality of control circuits which transmit the address signals to the word line driving circuits or interrupt transmission of the address signals according to the logic level of the global word line. Each of the word line driving circuits includes a first transistor which maintains the voltage of the respective sub word line at a first voltage and a second transistor which maintains the voltage of the sub word line at the first voltage or a second voltage.
摘要翻译：一个方面的半导体存储器件包括包括n个全局字线的存储单元块，以及n个全局字线中的每一个的对应m个子字线，其中n和m是自然数。存储装置还包括多个字线驱动电路，其分别根据每个对应的全局字线和输入的地址信号的逻辑电平分别控制子字线的电压，以及多个控制电路，其将地址信号发送到字线驱动电路或根据全局字线的逻辑电平中断地址信号的传输。每个字线驱动电路包括将相应子字线的电压维持在第一电压的第一晶体管和将子字线的电压维持在第一电压或第二电压的第二晶体管。

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