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31. 发明申请

WO2006079097A1 STRUCTURE AND METHOD OF MAKING INTERCONNECT ELEMENT HAVING METAL TRACES EMBEDDED IN SUFACE OF DIELECTRIC 审中-公开
标题翻译：具有嵌入在电介质的金属轨迹的互连元件的结构和方法
公开(公告)号：WO2006079097A1
公开(公告)日：2006-07-27
申请号：PCT/US2006/002597
申请日：2006-01-24
申请人： SOCKETSTRATE, INC. , NORTH CORPORATION , KOTAKE, Hideki , HYODO, Kiyoshi , KUROSAWA, Inetaro , HASHIMOTO, Yukio , YOSHINO, Toku , IIJIMA, Tomoo
发明人： KOTAKE, Hideki , HYODO, Kiyoshi , KUROSAWA, Inetaro , HASHIMOTO, Yukio , YOSHINO, Toku , IIJIMA, Tomoo
IPC分类号： H05K3/42
CPC分类号： H05K3/4647 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H05K3/107 , H05K3/20 , H05K3/428 , H05K3/4602 , H05K3/4614 , H05K2201/0376 , H05K2201/0379 , H05K2203/061 , H05K2203/0733 , H05K2203/1536 , H01L2924/00
摘要： An interconnect element (201) is provided which includes a dielectric element (210) having a major surface. Metal interconnect patterns (208, 208') are embedded in recesses which extend inwardly from the major surface, the outer surfaces of the interconnect patterns being substantially co-planar with the major surface and extending in one or more directions of the major surface. A projecting conductive film (220) extends over the major surface in at least one direction parallel to a plane defined by the major surface such that it contacts the dielectric element (210) along at least a portion of the major surface and conductively contacts an outer surface of at least one of the metal interconnect patterns (208').
摘要翻译：提供了互连元件（201），其包括具有主表面的电介质元件（210）。金属互连图案（208,208'）嵌入从主表面向内延伸的凹槽中，互连图案的外表面与主表面基本共面并在主表面的一个或多个方向上延伸。突出的导电膜（220）在平行于由主表面限定的平面的至少一个方向上在主表面上延伸，使得其沿着主表面的至少一部分接触电介质元件（210）并且导电地接触外表面至少一个金属互连图案（208'）的表面。

32. 发明申请

WO2006020744A2 STRUCTURE AND METHOD OF FORMING CAPPED CHIPS 审中-公开
标题翻译：结构和形成CAPPED CHIPS的方法
公开(公告)号：WO2006020744A2
公开(公告)日：2006-02-23
申请号：PCT/US2005/028492
申请日：2005-08-11
申请人： TESSERA, INC. , HABA, Belgacem , BEROZ, Masud , URBISH, Glenn , TUCKERMAN, David, B.
发明人： HABA, Belgacem , BEROZ, Masud , URBISH, Glenn , TUCKERMAN, David, B.
IPC分类号： B81B7/00
CPC分类号： B81B7/007 , H03H3/02 , H03H9/0547 , H03H9/059 , H03H9/1057 , H03H9/1092
摘要： As disclosed herein, structures and methods are provided for forming capped chips. As provided by the disclosed method, a metal base pattern (26) is formed on a chip (8) insulated from wiring (11) of the chip, and a cap (42) is formed including a metal. The cap (42) is joined to the metal base pattern (26) on the chip to form the capped chip (48). In one embodiment, a front surface (9) of the chip is exposed which extends from a contact (14) or (16) of the chip to an edge (13) of the chip (8). In another embodiment, a conductive connection is formed to the contact (14) or (16), the conductive connection extending from the contact to a terminal (46) at an exposed plane (49) above the front surface (9) of the chip (8).
摘要翻译：如本文所公开的，提供了用于形成加盖芯片的结构和方法。如公开的方法所提供的，在与芯片的布线（11）绝缘的芯片（8）上形成金属基底图案（26），并且形成包括金属的盖（42）。盖（42）连接到芯片上的金属基底图案（26）以形成盖帽芯片（48）。在一个实施例中，芯片的前表面（9）被暴露，其从芯片的触点（14）或（16）延伸到芯片（8）的边缘（13）。在另一个实施例中，导电连接形成于触点（14）或（16），导电连接在芯片的前表面（9）上方的暴露平面（49）处从触点延伸至端子（46）（8）。

33. 发明申请

WO2013052441A2 STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS 审中-公开
标题翻译：无窗口的线束组件的最小化
公开(公告)号：WO2013052441A2
公开(公告)日：2013-04-11
申请号：PCT/US2012/058398
申请日：2012-10-02
申请人： INVENSAS CORPORATION
发明人： CRISP, Richard, Dewitt , ZOHNI, Wael , HABA, Belgacem , LAMBRECHT, Frank
CPC分类号： G11C5/04 , G11C5/02 , G11C5/063 , G11C5/066 , H01L23/13 , H01L23/3128 , H01L23/36 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L2224/02375 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05569 , H01L2224/0557 , H01L2224/06155 , H01L2224/06156 , H01L2224/06165 , H01L2224/06179 , H01L2224/06181 , H01L2224/06515 , H01L2224/12105 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/48471 , H01L2224/49113 , H01L2224/49175 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06558 , H01L2225/06562 , H01L2225/06565 , H01L2225/06568 , H01L2225/06575 , H01L2225/06589 , H01L2924/00014 , H01L2924/01322 , H01L2924/10161 , H01L2924/1434 , H01L2924/1435 , H01L2924/1436 , H01L2924/1438 , H01L2924/15172 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/181 , H01L2924/18161 , H01L2924/3011 , H05K1/181 , H05K2201/09227 , H05K2201/10159 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A microelectronic package (100) can include a plurality of vertically stacked semiconductor chips 632, 637, the front face of at least one chip facing away from a first substrate surface (108), one or more columns (138, 143) of contacts (132) extending in a first direction (142) along surface (108). Columns (104A, 107B, 109A, 109B) of terminals (105 107) exposed at a second substrate surface (110) extend in the first direction. First terminals (105) disposed in a central region (112) of surface (110) which has width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the at least one semiconductor chip can intersect the central region.
摘要翻译：微电子封装（100）可以包括多个垂直堆叠的半导体芯片632,637，至少一个芯片的前表面背离第一衬底表面（108），一个或多个接触柱（138,143） 132）沿着第一方向（142）沿着表面（108）延伸。在第二基板表面（110）处露出的端子（1057a）的列（104A，107B，109A，109B）在第一方向上延伸。布置在表面（110）的中心区域（112）中的第一端子（105）可以被配置为承载地址（110）的宽度（152）不大于端子列的最小间距（150）的三分之一倍的距离）用于确定可寻址存储器位置的信息。至少一个半导体芯片的轴向平面可以与中心区域相交。

34. 发明申请

WO2013052368A2 STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS 审中-公开
标题翻译： STUB最小化使用无需WINDOWS的WIREBOND组件的端子套件
公开(公告)号：WO2013052368A2
公开(公告)日：2013-04-11
申请号：PCT/US2012/057810
申请日：2012-09-28
申请人： INVENSAS CORPORATION
发明人： CRISP, Richard, Dewitt , ZOHNI, Wael , HABA, Beigacem , LAMBRECHT, Frank
CPC分类号： G11C5/02 , G11C5/04 , G11C5/063 , H01L23/49838 , H01L23/50 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/0557 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/16145 , H01L2224/16225 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/49113 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06551 , H01L2225/06558 , H01L2225/06562 , H01L2225/06589 , H01L2225/1023 , H01L2225/107 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/19105 , H01L2924/3011 , H05K1/181 , H05K2201/09227 , H05K2201/10159 , Y02P70/611 , H01L2924/00012 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/05599
摘要： A microelectronic element (101) having memory storage array function has a front face (105) facing away from a substrate (102) of a microelectronic package (100), and is electrically connected with the substrate through conductive structure (112) extending above the front face (105). First terminals (104) are disposed at locations within first and second sets (114, 124) thereof disposed on respective first and second opposite sides of a theoretical axis (132). The first terminals of each set are configured to carry address information usable to determine an addressable memory location of a memory storage array of the microelectronic element. The first terminals in the first set (114) have signal assignments which are a mirror image of the signal assignments of the first terminals in the second set (124).
摘要翻译：具有存储器存储阵列功能的微电子元件（101）具有背向微电子封装（100）的衬底（102）的正面（105），并且通过导电结构（112）在正面（105）上方延伸。第一端子（104）设置在第一和第二组（114,124）内的位于理论轴线（132）的相应第一和第二相对侧上的位置处。每组的第一端子被配置为携带可用于确定微电子元件的存储器存储阵列的可寻址存储器位置的地址信息。第一组（114）中的第一终端具有信号分配，这些信号分配是第二组（124）中第一终端的信号分配的镜像。

35. 发明申请

WO2012012323A2 STACKABLE MOLDED MICROELECTRONIC PACKAGES 审中-公开
标题翻译：可堆叠成型的微电子封装
公开(公告)号：WO2012012323A2
公开(公告)日：2012-01-26
申请号：PCT/US2011/044346
申请日：2011-07-18
申请人： TESSERA, INC. , HABA, Belgacem
发明人： HABA, Belgacem
IPC分类号： H01L23/498 , H01L21/56 , H01L21/50
CPC分类号： H01L25/0657 , H01L21/56 , H01L21/565 , H01L23/3121 , H01L23/3128 , H01L23/315 , H01L23/3157 , H01L23/49805 , H01L23/49811 , H01L23/49838 , H01L24/14 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/105 , H01L25/50 , H01L2224/05554 , H01L2224/1401 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06548 , H01L2225/06565 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/10161 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599 , H01L2224/85399
摘要： A microelectronic package has a microelectronic element 110 overlying or mounted to a first surface 102 of a substrate 100 and substantially rigid conductive posts 106 projecting above the first surface or projecting above a second surface 104 of the substrate remote therefrom. Conductive elements 108 exposed at a surface of the substrate opposite the surface above which the conductive posts project are electrically interconnected with the microelectronic element. An encapsulant 130 overlies at least a portion of the microelectronic element 110 and the surface 102 of the substrate 100 above which the conductive posts 106 project, the encapsulant having a recess 336 or one or more openings 136, 236 each permitting at least one electrical connection to be made to at least one conductive post. At least some conductive posts 106 are electrically insulated from one another and adapted to simultaneously carry different electric potentials. In particular embodiments, the openings 136, 140, 146, 236 in the encapsulant 130 at least partially expose conductive masses 144 joined to posts, fully expose top surfaces 126 of posts 106 and partially expose edge surfaces 138 of posts, or may only partially expose top surfaces 126 of posts.
摘要翻译：微电子封装具有覆盖或安装到衬底100的第一表面102上的微电子元件110，以及基本上刚性的导电柱106，突出在第一表面上方或突出在远离其的衬底的第二表面104上方。导电元件108暴露在基板的与导电柱突出的表面相对的表面，导电柱突出的位置与微电子元件电互连。密封剂130覆盖微电子元件110和衬底100的表面102的至少一部分，导电柱106突出于其上，密封剂具有凹部336或一个或多个开口136,236，每个允许至少一个电连接制成至少一个导电柱。至少一些导电柱106彼此电绝缘并适于同时携带不同的电位。在具体实施例中，密封剂130中的开口136,140,146,236至少部分地暴露接合到柱的导电块144，完全暴露柱106的顶表面126并且部分地暴露柱的边缘表面138，或者仅部分地暴露柱的顶面126。

36. 发明申请

WO2012012321A2 STACKABLE MOLDED MICROELECTRONIC PACKAGES WITH AREA ARRAY UNIT CONNECTORS 审中-公开
标题翻译：具有区域阵列连接器的可堆叠成型的微电子封装
公开(公告)号：WO2012012321A2
公开(公告)日：2012-01-26
申请号：PCT/US2011/044342
申请日：2011-07-18
申请人： TESSERA, INC. , HABA, Belgacem
发明人： HABA, Belgacem
IPC分类号： H01L23/52 , H01L21/56
CPC分类号： H01L25/0657 , H01L21/561 , H01L21/563 , H01L21/565 , H01L23/3107 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/66 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/92 , H01L24/97 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2223/6611 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48105 , H01L2224/48145 , H01L2224/48225 , H01L2224/48227 , H01L2224/4911 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/81191 , H01L2224/81801 , H01L2224/8385 , H01L2224/92125 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06565 , H01L2225/06568 , H01L2225/06572 , H01L2225/1023 , H01L2225/1029 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/00014 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07811 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/3011 , H01L2924/351 , H01L2224/81 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/83851 , H01L2224/45099
摘要： A microelectronic package (290) having a (substrate 230), a microelectronic element (170), e.g., a chip, and terminals (240) can have conductive elements (238) electrically connected with element contacts of the chip and contacts of the substrate. Conductive elements can be electrically insulated from one another for simultaneously carrying different electric potentials. An encapsulant (201) can overlie the first surface (136) of the substrate and at least a portion of a face (672) of the microelectronic element remote from the substrate, and may have a major surface (200) above the microelectronic element. A plurality of package contacts (120, 220, 408, 410, 427) can overlie a face (672) of the microelectronic element remote from the substrate. The package contacts, e.g., conductive masses (410), substantially rigid posts (120, 220), can be electrically interconnected with terminals (240) of the substrate (230), such as through the conductive elements. The package contacts can have top surfaces (121) at least partially exposed at the major (surface 200) of the encapsulant (201).
摘要翻译：具有（衬底230），微电子元件（170），例如芯片和端子（240）的微电子封装（290）可以具有与芯片的元件触点和衬底的触点电连接的导电元件（238）。导电元件可以彼此电绝缘以同时承载不同的电位。密封剂（201）可以覆盖在衬底的第一表面（136）上，并且微电子元件的面（672）的至少一部分远离衬底，并且可以在微电子元件上方具有主表面（200）。多个封装触点（120,220,408,410,427）可以覆盖远离衬底的微电子元件的面（672）。诸如导电块（410），基本上刚性的柱（120,220）的封装接触可以例如通过导电元件与衬底（230）的端子（240）电互连。封装接触件可以具有至少部分地暴露在密封剂（201）的主表面（200）处的顶表面（121）。

37. 发明申请

WO2010021685A1 MICROELECTRONIC SUBSTRATE HAVING METAL POSTS JOINED THERETO USING BOND LAYER 审中-公开
标题翻译：使用BOND层加入金属片的微电子基板
公开(公告)号：WO2010021685A1
公开(公告)日：2010-02-25
申请号：PCT/US2009/004694
申请日：2009-08-14
申请人： TESSERA INTERCONNECT MATERIALS, INC. , HABA, Belgacem , RYU, Chang, Myung , ENDO, Kimitaka , WADE, Christopher, Paul
发明人： HABA, Belgacem , RYU, Chang, Myung , ENDO, Kimitaka , WADE, Christopher, Paul
IPC分类号： H01L23/498 , H01L21/48
CPC分类号： H01L24/89 , H01L21/4853 , H01L23/49811 , H01L23/49816 , H01L24/16 , H01L24/81 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/13017 , H01L2224/13021 , H01L2224/13609 , H01L2224/81192 , H01L2224/81801 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/07811 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An interconnection element 110 can include a substrate, e.g., a connection substrate, element of a package, circuit panel or microelectronic substrate, e.g., semiconductor chip, the substrate having a plurality of metal conductive elements such as conductive pads 112, contacts, bond pads, traces, or the like exposed at the surface. A plurality of solid metal posts 130 may overlie and project away from respective ones of the conductive elements. An intermetallic layer 121 can be disposed between the posts and the conductive elements, such layer providing electrically conductive interconnection between the posts 130 and the conductive elements 112. Bases of the posts adjacent to the intermetallic layer can be aligned with the intermetallic layer.
摘要翻译：互连元件110可以包括衬底，例如连接衬底，封装的元件，电路板或微电子衬底，例如半导体芯片，衬底具有多个金属导电元件，例如导电焊盘112，触点，接合焊盘，痕迹等暴露在表面。多个固体金属柱130可以覆盖并突出远离相应的导电元件。金属间层121可以设置在柱和导电元件之间，这样的层提供柱130和导电元件112之间的导电互连。邻接金属间层的柱的基座可以与金属间层对准。

38. 发明申请

WO2008033552A2 SYSTEM AND METHOD FOR DISTRIBUTED MEDIA STREAMING AND SHARING 审中-公开
标题翻译：用于分布式媒体流和共享的系统和方法
公开(公告)号：WO2008033552A2
公开(公告)日：2008-03-20
申请号：PCT/US2007/020112
申请日：2007-09-12
申请人： IWATCHNOW INC. , COLLAZO, Caesar
发明人： COLLAZO, Caesar
CPC分类号： H04L67/104 , H04L29/06027 , H04L63/0428 , H04L63/101 , H04L63/123 , H04L63/126 , H04L65/607 , H04L67/06
摘要： A distributed media sharing and streaming system and method is disclosed, wherein an encrypted resident micro web server (100) stores media files (320) in a universal media format including an embedded, automated streaming media player (230), where the micro web server further fingerprints and authenticates media file contents, indexes media files, manages user permission, group permissions and sharing functionality, shares authenticated media files (320) over a network (40) via a distributed system employing other users on the network with the resident micro web server (100) and the authenticated media file (320), shares media file and user information with a central index server, and streams authenticated media files to a sharing user using an embedded streaming media player (230) regardless of whether the sharing user has the micro web server or any particular media codec.
摘要翻译：公开了一种分布式媒体共享和流传输系统和方法，其中加密的驻留微型网络服务器（100）以包括嵌入式自动流媒体播放器（230）的通用媒体格式存储媒体文件（320），其中微型web服务器进一步指纹和认证媒体文件内容，索引媒体文件，管理用户权限，组权限和共享功能，通过使用驻留微网的网络上的其他用户的分布式系统在网络（40）上共享认证媒体文件（320）服务器（100）和经认证的媒体文件（320）与中央索引服务器共享媒体文件和用户信息，并且使用嵌入式流媒体播放器（230）将认证媒体文件流传送给共享用户，而不管共享用户是否具有微型Web服务器或任何特定的媒体编解码器。

39. 发明申请

WO2006039633A2 STRUCTURE AND METHOD OF MAKING INTERCONNECT ELEMENT, AND MULTILAYER WIRING BOARD INCLUDING THE INTERCONNECT ELEMENT 审中-公开
标题翻译：制造互连元件的结构和方法以及包括互连元件的多层布线板
公开(公告)号：WO2006039633A2
公开(公告)日：2006-04-13
申请号：PCT/US2005/035459
申请日：2005-09-30
申请人： SOCKETSTRATE, INC. , NORTH CORPORATION , ENDO, Kimitaka , MASUDA, Kenji , SHIMADA, Tomokazu
发明人： ENDO, Kimitaka , MASUDA, Kenji , SHIMADA, Tomokazu
IPC分类号： H01L21/48 , H01L23/498 , H01L23/538 , H05K3/46
CPC分类号： H05K3/4617 , H01L21/4857 , H01L23/49822 , H01L23/5383 , H01L2924/0002 , H05K3/064 , H05K3/205 , H05K3/423 , H05K3/4647 , H05K2203/0384 , H05K2203/0542 , H05K2203/0733 , Y10S438/931 , Y10T29/49124 , H01L2924/00
摘要： An interconnect element (2) is provided which includes a dielectric element (4) having a first major surface, a second major surface remote from the first major surface, and a plurality of recesses extending inwardly from the first major surface. A plurality of metal traces (6), (6a) are embedded in the plurality of recesses, the metal traces having outer surfaces substantially co-planar with the first major surface and inner surfaces remote from the outer surfaces. A plurality of posts (8) extend from the inner surfaces of the plurality of metal traces (6), (6a) through the dielectric element (4), the plurality of posts having tops exposed at the second major surface. A multilayer wiring board (12) including a plurality of such interconnect elements (2) is also provided, as, well as various methods for making such interconnect elements and multilayer wiring boards.
摘要翻译：提供互连元件（2），其包括具有第一主表面的电介质元件（4），远离第一主表面的第二主表面和从第一主表面向内延伸的多个凹槽。多个金属迹线（6），（6a）嵌入在多个凹部中，金属迹线具有与第一主表面和远离外表面的内表面基本共面的外表面。多个柱（8）从多个金属迹线（6），（6a）的内表面延伸穿过电介质元件（4），多个柱具有在第二主表面处露出的顶部。还提供了包括多个这种互连元件（2）的多层布线板（12）以及用于制造这种互连元件和多层布线板的各种方法。

40. 发明申请

WO2013052448A1 STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS 审中-公开
标题翻译：无窗口的线束组件的最小化
公开(公告)号：WO2013052448A1
公开(公告)日：2013-04-11
申请号：PCT/US2012/058407
申请日：2012-10-02
申请人： INVENSAS CORPORATION
发明人： CRISP, Richard, Dewitt , ZOHNI, Wael , HABA, Belgacem , LAMBRECHT, Frank
IPC分类号： H01L25/065 , H01L23/13 , G11C5/02 , G11C5/04 , G11C5/06
CPC分类号： G11C5/04 , G11C5/02 , G11C5/063 , G11C5/066 , H01L23/13 , H01L23/3128 , H01L23/36 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L2224/02375 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05569 , H01L2224/0557 , H01L2224/06155 , H01L2224/06156 , H01L2224/06165 , H01L2224/06179 , H01L2224/06181 , H01L2224/06515 , H01L2224/12105 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/48471 , H01L2224/49113 , H01L2224/49175 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06558 , H01L2225/06562 , H01L2225/06565 , H01L2225/06568 , H01L2225/06575 , H01L2225/06589 , H01L2924/00014 , H01L2924/01322 , H01L2924/10161 , H01L2924/1434 , H01L2924/1435 , H01L2924/1436 , H01L2924/1438 , H01L2924/15172 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/181 , H01L2924/18161 , H01L2924/3011 , H05K1/181 , H05K2201/09227 , H05K2201/10159 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up above a first surface (108) of a substrate (102), one or more columns (138, 140) of contacts (132) extending in a first direction (142) along the microelectronic element front face. Columns (104A, 105B, 107A, 107B) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction. First terminals (105) exposed at surface (110) in a central region (112) thereof having width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.
摘要翻译：微电子组件（300）或系统（1500）包括至少一个微电子封装（100），所述微电子封装（100）具有面向上安装在衬底（102）的第一表面（108）上方的微电子元件（130），一个或多个柱，140）沿着所述微电子元件正面在第一方向（142）延伸的触点（132）。在基板的第二表面（110）处露出的端子（1057a）的列（104A，105B，107A，107B）沿第一方向延伸。具有宽度（152）不大于终端列的最小间距（150）的三分之一倍的中心区域（112）的表面（110）处的第一端子（105）可被配置为承载地址用于确定可寻址存储器位置的信息。微电子元件的轴向平面可以与中心区域相交。

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