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    • 31. 发明申请
    • METHOD AND SYSTEM FOR ACCELERATED ACCESS TO A MEMORY
    • 用于加速访问存储器的方法和系统
    • WO2002095601A1
    • 2002-11-28
    • PCT/IB2002/001794
    • 2002-05-21
    • KONINKLIJKE PHILIPS ELECTRONICS N.V.MUTZ, StephaneDESMICHT, EricNOUVET, Thierry
    • MUTZ, StephaneDESMICHT, EricNOUVET, Thierry
    • G06F13/16
    • G06F13/1626
    • Method of transferring data between a memory comprising several banks and a data processing circuit, the method comprising the steps of: producing access requests (46, 47) defining each time a type of access and designating one or several memory locations (46a-d, 47a-b) arranged in accordance with a sequence suitable for said request; processing the requests in accordance with a successive sequence so as to transfer, for each processed request, data from the designated memory location to the data processing circuit, or vice versa; the processing of a request (46) designating memory locations (46a, 46b, 46c, 46d) associated with several banks (A, B, A, B) authorizing a transfer of data between the interface and the memory locations in a sequence which is different from the sequence associated with said request.
    • 在包括多个存储体的存储器和数据处理电路之间传送数据的方法,所述方法包括以下步骤:产生访问请求(46,47),每次访问的类型和指定一个或多个存储器位置(46​​a-d, 47a-b)根据适合于所述请求的顺序排列; 根据连续的顺序对请求进行处理,以便为每个处理的请求传送从指定的存储单元到数据处理电路的数据,反之亦然; 指定与几个银行(A,B,A,B)相关联的存储器位置(46​​a,46b,46c,46d)的请求(46)的处理,该存储器位置(A,B,A,B)授权在接口和存储器位置之间的数据传输, 不同于与所述请求相关联的序列。
    • 33. 发明申请
    • COMMUNICATION SYSTEM
    • 通讯系统
    • WO2003060737A1
    • 2003-07-24
    • PCT/IB2002/005682
    • 2002-12-20
    • KONINKLIJKE PHILIPS ELECTRONICS N.V.BENARD, FrançoisDUTILLEUL, Frederic
    • BENARD, FrançoisDUTILLEUL, Frederic
    • G06F13/42
    • G06F13/4282
    • The invention relates to a communication system comprising a control unit (100), a plurality of circuits (101-104) intended to be accessed by the control unit and a bus (105) intended to allow a data exchange between the control unit and an accessed circuit. In order to avoid that the circuits have specific address, they are accessed by the control unit in a predefined accessing order, and the system comprises means for changing an address of a circuit so that an accessed circuit has a predefined address. The circuits having no specific addresses, such a communication system is particularly easy to create or modify. The invention is particularly relevant for a dispatching station for TV signals.
    • 本发明涉及一种通信系统,包括控制单元(100),旨在由控制单元访问的多个电路(101-104)以及旨在允许控制单元和控制单元之间的数据交换的总线(105) 访问电路。 为了避免电路具有特定的地址,它们以预定的访问顺序由控制单元访问,并且系统包括用于改变电路的地址以使得所访问的电路具有预定义地址的装置。 没有特定地址的电路,这种通信系统特别容易创建或修改。 本发明特别适用于TV信号的调度台。
    • 34. 发明申请
    • METHOD FOR DECODING DATA USING WINDOWS OF DATA
    • 使用数据窗口解码数据的方法
    • WO2003056707A1
    • 2003-07-10
    • PCT/IB2002/005696
    • 2002-12-20
    • KONINKLIJKE PHILIPS ELECTRONICS N.V.CHARPENTIER, Sebastien
    • CHARPENTIER, Sebastien
    • H03M13/37
    • H03M13/37
    • The present invention relates to a method using windows of data, a window (w) comprising data to be written and to be read and having a size. It is characterized in that it comprises:* A step of writing a current window of data into a unique buffer (BUF) in a first address direction, said first address direction being at an opposite direction from an address direction of the writing of a preceding window of data, said writing of said current window beginning at an address where no data of the preceding window of data have been written, said buffer (BUF) having a length greater than the maximum size of the windows of data, and* A step of reading the data of said preceding window of data from said unique buffer (BUF), from a reading address equal to a last written address of the same preceding window of data, said reading being made simultaneously to said writing of the current window of data and in the same first address direction.
    • 本发明涉及一种使用数据窗口的方法,包括要被写入并被读取且具有大小的数据的窗口(w)。 其特征在于它包括:*将当前数据窗口以第一地址方向写入唯一缓冲器(BUF)的步骤,所述第一地址方向与前一个写入的地址方向相反的方向 从数据窗口开始的所述当前窗口的写入开始于没有前面的数据窗口的数据的地址,所述缓冲器(BUF)的长度大于数据窗口的最大大小,以及*步骤 从与所述同一先前数据窗口的最后写入地址相等的读取地址读取来自所述唯一缓冲器(BUF)的所述前一数据窗口的数据的所述读取同时进行所述当前数据窗口的写入 并且在相同的第一地址方向。
    • 37. 发明申请
    • SYSTEM FOR TRANSMITTING ADDITIONAL INFORMATION VIA A NETWORK
    • 通过网络发送附加信息的系统
    • WO2003051016A1
    • 2003-06-19
    • PCT/IB2002/005242
    • 2002-12-06
    • KONINKLIJKE PHILIPS ELECTRONICS N.V.LAMY, CatherineMERIGEAULT, SandrineMEILHAC, Lisa
    • LAMY, CatherineMERIGEAULT, SandrineMEILHAC, Lisa
    • H04L29/06
    • H04N21/654H04L69/16H04L69/161H04L69/164H04L69/167H04L69/22H04L69/32H04N21/234327H04N21/2383H04N21/4382H04N21/6332H04N21/6377H04N21/6437H04N21/64707H04N21/6473H04N21/64753H04N21/64761H04N21/658
    • The present invention relates to a transmission system for transmitting source application data units to a destination application via a network comprising a plurality of network protocol stacks. Such a transmission system provides a solution for transmitting additional information from a layer of a first network protocol stack to a layer of a second network protocol stack, without disturbing the way in which ordinary streams are processed. To this end, it further comprises: generating means for generating additional information at a layer of a first network protocol stack to be sent to a layer of a second network protocol stack via at least said first and second network protocol stacks, adapting means for converting said additional information into at least one additional data unit compliant with network protocol rules, marking means for marking said additional data units, retrieving means for retrieving said additional information within said additional data units when said additional data units arrive at said layer of said second network protocol stack. More generally, the invention deals with all the possible exchanges of additional information between layers of network protocol stacks within a transmission system. Said transmission system may also include some routers.
    • 本发明涉及一种用于经由包括多个网络协议栈的网络将源应用数据单元发送到目的地应用的传输系统。 这样的传输系统提供了用于将附加信息从第一网络协议栈的层传送到第二网络协议栈的层的解决方案,而不会干扰处理普通流的方式。 为此,它还包括:产生装置,用于在第一网络协议栈的层产生附加信息,以经由至少所述第一和第二网络协议栈发送到第二网络协议栈的层,适配装置,用于转换 将附加信息传送到符合网络协议规则的至少一个附加数据单元,用于标记所述附加数据单元的标记装置,当所述附加数据单元到达所述第二网络的所述层时,在所述附加数据单元内检索所述附加信息的检索装置 协议栈 更一般地,本发明处理在传输系统内的网络协议栈层之间的所有可能的附加信息交换。 所述传输系统还可以包括一些路由器。
    • 38. 发明申请
    • CLOCK DOMAIN CROSSING FIFO
    • 时域交叉FIFO
    • WO2003039061A2
    • 2003-05-08
    • PCT/IB2002/004076
    • 2002-10-02
    • KONINKLIJKE PHILIPS ELECTRONICS N.V.
    • PONTIUS, Timothy, A.PAYNE, Robert, L.EVOY, David, R.
    • H04L7/02
    • H04L7/02G06F5/10G06F2205/102H04L7/0008H04L7/005
    • A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.
    • 提供了将数据从源时钟域传递到非同步接收时钟域的方法和装置。 位于源时钟域的第一处理电路将写入地址信息与数据相连接,并且时钟发生器在与源时钟同步的源时钟域中生成发送时钟信号。 第一处理电路将时钟信号和具有链接的写入地址信息的数据发送到接收时钟域中的第二处理电路。 在接收时钟域中,第二处理电路将数据写入指定对应于链接的写入地址信息的存储元件的地址。 第二处理电路响应于来自源时钟域的写入使能信号将数据与伴随的发送时钟信号同步地存储到存储元件中,并且从存储元件读出与接收域时钟同步的数据。
    • 39. 发明申请
    • VIDEO ARTIFACT IDENTIFICATION AND COUNTING
    • 视频伪装身份识别和计数
    • WO2003036986A2
    • 2003-05-01
    • PCT/IB2002/004222
    • 2002-10-14
    • KONINKLIJKE PHILIPS ELECTRONICS N.V.
    • LIN, Chien-HsinYANG, Chang-Ming
    • H04N7/30
    • H04N19/527H04N19/86
    • Artifact detection and counting is enhanced using looping in both the horizontal and vertical direction is enhanced via a reduced bandwidth for accumulation of count values into count table entries. According to an example embodiment of the present invention, first and second loops are made for horizontal and vertical count table entries. Quotient and remainder values of a detected artifact value are used for increasing count table entries in the first looping pass, and the count table entries are increased using the quotient value in the second loop. The table increase in the first loop is limited to the length of the remainder value, and the table increase in the second loop is limited to the length of the row or column in the count table being used. In this manner, latency for additions to the count table and the bandwidth for making the additions are reduced, relative to conventional applications. In addition, each entry into the table can be reduced to one addition.
    • 通过减少的带宽将计数值累计到计数表条目中,使用水平和垂直方向上的循环增强伪影检测和计数。 根据本发明的示例实施例,为水平和垂直计数表条目制作第一和第二环。 检测到的工件值的商数和余数值用于增加第一个循环传递中的计数表条目,并且使用第二个循环中的商值增加计数表条目。 第一个循环中的表增加限于剩余值的长度,而第二个循环中的表增加限于正在使用的计数表中的行或列的长度。 以这种方式,与常规应用相比,添加到计数表的延迟和用于进行添加的带宽被减少。 另外,表中的每个条目都可以减少一个。
    • 40. 发明申请
    • MICRO-MACHINED ULTRASONIC TRANSDUCER (MUT) ARRAY
    • 微机械超声换能器(MUT)阵列
    • WO2003011749A2
    • 2003-02-13
    • PCT/IB2002/003187
    • 2002-07-26
    • KONINKLIJKE PHILIPS ELECTRONICS N.V.
    • MILLER, David, G.
    • B81B7/04
    • B06B1/0292
    • An ultrasonic transducer array comprising individual transmit MUT elements and receive MUT elements includes the transmit MUT elements and the receive MUT elements distributed in two dimensions over the array. By using different MUT elements for transmit and receive operation, each MUT element can be independently optimized for either transmit operation or receive operation. Furthermore, by independently optimizing the MUT elements for either transmit or receive operation, the same bias voltage can be applied to the MUT elements, thereby simplifying the bias circuitry associated with the MUT transducer array. Alternatively, because the MUT elements are independently optimized for transmit and receive, different bias voltages can be applied to the transmit and receive elements, thus providing further optimization of the elements.
    • 包括单独的发射MUT元件和接收MUT元件的超声换能器阵列包括发射MUT元件和在阵列上以二维方式分布的接收MUT元件。 通过使用不同的MUT元件进行发送和接收操作,每个MUT元件可以独立地针对发送操作或接收操作进行优化。 此外,通过针对发送或接收操作独立地优化MUT元件,可以向MUT元件施加相同的偏置电压,由此简化与MUT换能器阵列相关联的偏置电路。 或者,因为MUT元件独立地针对发送和接收进行优化,所以可以将不同的偏置电压施加到发送和接收元件,从而进一步优化元件。