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31. 发明公开

EP1153438A2 OFFSET DRAIN FERMI-THRESHOLD FIELD EFFECT TRANSISTORS 审中-公开
标题翻译： FERMI阈值电压场效应晶体管，抵消漏
公开(公告)号：EP1153438A2
公开(公告)日：2001-11-14
申请号：EP99961583.4
申请日：1999-11-04
申请人： THUNDERBIRD TECHNOLOGIES, INC.
发明人： RICHARDS, William, R., Jr. , DENNEN, Michael, W.
IPC分类号： H01L29/78
CPC分类号： H01L29/7838 , H01L29/7835
摘要： An offset drain Fermi-threshold field effect transistor (Fermi-FET) includes spaced apart source and drain regions in an integrated circuit substrate, and a Fermi-FET channel in the integrated circuit substrate, between the spaced apart source and drain regions. A gate insulating layer is on the integrated circuit substrate between the spaced apart source and drain regions, and a gate electrode is on the gate insulating layer. The gate electrode is closer to the source region than to the drain region. Stated differently, the drain region is spaced farther away from the gate electrode than the source region. The offset drain Fermi-FET can introduce a drift region between the drain region and the Fermi-FET channel that can provide the high voltage and/or high frequency Fermi-FETs, while retaining the Fermi-FET advantages in the channel.

32. 发明授权

EP0463067B1 FERMI THRESHOLD FIELD EFFECT TRANSISTOR 有权
标题翻译：费米阈值电压场效应晶体管
公开(公告)号：EP0463067B1
公开(公告)日：1996-06-05
申请号：EP90905155.9
申请日：1990-03-01
申请人： THUNDERBIRD TECHNOLOGIES, INC.
发明人： VINAL, Albert, W.
IPC分类号： H01L29/36 , H01L29/10 , H01L29/78 , H01L29/49
CPC分类号： H01L29/4916 , H01L29/4925 , H01L29/7831 , H01L29/7836 , H01L29/7838
摘要： A field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the semiconductor material. The FET, referred to as a Fermi Threshold FET or Fermi-FET, has a threshold voltage which is independent of oxide thickness, channel length, drain voltage and substrate doping, the vertical electric field in the channel becomes zero, thereby maximizing carrier mobility, and minimizing hot electron effects. A high speed device, substantially independent of device dimensions is thereby provided, which may be manufactured using relaxed groundrules, to provide low cost, high yield devices. Temperature dependence of threshold voltage may also be eliminated by providing a semiconductor gate contact which neutralizes the effect of substrate contact potential. Source and drain subdiffusion regions may be provided to simultaneously maximize the punch-through and impact ionization voltages of the devices, so that short channel devices do not require scaled-down power supply voltages. Multi gate devices may be provided. An accelerator gate, adjacent the drain, may further improve performance. The Fermi-FET criteria may be maintained, while allowing for a deep channel by providing a substrate contact for the Fermi-FET and applying a substrate bias to this contact. Substrate enhancement pocket regions adjacent the source and drain regions may be provided to produce a continuous depletion region under the source, drain and channel regions to thereby minimize punch-through effects.

33. 发明授权

EP0569540B1 COMPLEMENTARY LOGIC INPUT PARALLEL (CLIP) LOGIC CIRCUIT FAMILY 有权转让
标题翻译：互补逻辑家族具有平行逻辑输入。
公开(公告)号：EP0569540B1
公开(公告)日：1995-09-06
申请号：EP92906350.1
申请日：1992-01-31
申请人： THUNDERBIRD TECHNOLOGIES, INC.
发明人： VINAL, Albert W.
IPC分类号： H03K19/094 , H03K19/096 , H03K3/356 , H01L27/092
CPC分类号： H03K19/0963 , H01L27/092 , H03K3/356113 , H03K19/0948
摘要： A high speed low capacitance Complementary Logic Input Parallel (CLIP) logic family includes an FET driving stage (11), a complementary FET inverter (14), and at least one gating FET (13a-13b). The dimensions of the gating FET (13) are controlled relative to the dimensions of the driving stage FETs (11a-11f) to provide a high speed logic circuit. AND and OR CLIP logic circuits may be provided. A clocked CLIP logic circuit may be provided by adding a clocking FET. A latching clocked CLIP logic circuit may also be provided by adding a latching FET. In the latching clocked CLIP logic circuit, the gate output is latched so that it does not change during the clock period regardless of changes in the logic inputs of the circuit. The speed of the CLIP logic circuits may be further increased by including germanium in the channel of its P-channel FETs to thereby increase carrier mobility in the P-channel FETs. The N-channel FETs are free of germanium. The internal capacitance of the CLIP logic circuits is also decreased by using common diffusion regions in the integrated circuit for pairs of driving stage FETs. Common source and/or common drain diffusion regions may be used.

34. 发明授权

EP0467971B1 HIGH SPEED COMPLEMENTARY FIELD EFFECT TRANSISTOR LOGIC CIRCUITS 有权转让
标题翻译：互补场效应晶体管逻辑高速。
公开(公告)号：EP0467971B1
公开(公告)日：1994-10-19
申请号：EP90906650.8
申请日：1990-04-10
申请人： THUNDERBIRD TECHNOLOGIES, INC.
发明人： Vinal,Albert Watson
IPC分类号： H03K19/017 , H03K19/094
CPC分类号： H03K19/01721 , H03K19/09485
摘要： A high speed, high density, low power dissipation all parallel FET logic circuit includes a driving stage (11) having a plurality of parallel FETs of a first conductivity type (N) for receiving logic input signals and a load FET (13) of second conductivity type (P) connected to the common output (16) of the driving stage. A complementary FET inverter (14) including serially connected FETs of first and second conductivity type is connected to the common output (16) and the load FET (13). According to the invention the voltage transfer function of the complementary inverter (14) is skewed so that the product of the carrier mobility and the ratio of channel width to length of the inverter FET (14b) of the first conductivity type (N) is made substantially greater than the product of the carrier mobility and the ratio of channel width to length of the inverter FET (14a) of the second conductivity type (P). By skewing the voltage transfer function of the complementary inverter (14) the voltage lift-off interval is dramatically decreased, thereby improving the speed. AND and OR circuits and combined AND-OR circuits may be provided, having true and complement outputs. A multigate serial load transistor may further reduce power consumption.

35. 发明公开

EP0587753A1 DIFFERENTIAL LATCHING INVERTER AND RANDOM ACCESS MEMORY USING SAME 失效
标题翻译：差速锁反向调用，并可直接进入内存分配使用相同的设备。
公开(公告)号：EP0587753A1
公开(公告)日：1994-03-23
申请号：EP92913329.0
申请日：1992-05-28
申请人： THUNDERBIRD TECHNOLOGIES, INC.
发明人： VINAL, Albert, W.
IPC分类号： G11C11 , G11C7
CPC分类号： G11C7/065 , G11C11/419
摘要： Onduleur différentiel de verrouillage utilisant une paire d'onduleurs couplés transversalement et dotés d'une fonction de transfert de tension désaligné pour détecter rapidement un signal différentiel sur une paire de lignes de binaire dans une mémoire à accès sélectif, et pour assurer une détection rapide pendant une opération de lecture. Ledit onduleur différentiel de verrouillage peut également comprendre une paire symétrique d'onduleurs de sortie de fonction de transfert et des circuits d'excursion haute supplémentaires pour améliorer le fonctionnement rapide, et on peut l'utiliser dans une architecture de mémoire possédant des lignes de binaire primaires et des lignes de binaire de signaux, un onduleur différentiel de verrouillage étant relié à chaque paire de lignes de binaire de signaux. Les lignes de binaire primaires et les lignes de binaire de signaux sont couplées les unes aux autres pendant les opérations de lecture et d'écriture, sinon elles sont découplées. Les opérations de lecture et d'écriture peuvent être synchronisées de manière interne sans qu'il ne soit nécessaire de recourir à des impulsions d'horloge extérieures en réponse à un système rapide de détection de changements d'adresse, et à des signaux internes de synchronisation engendrés par des tampons de segments d'anneau à retard. Ainsi, on peut obtenir une mémoire à accès sélectif rapide et à faible consommation.

36. 发明授权

US5885876A Methods of fabricating short channel fermi-threshold field effect transistors including drain field termination region 失效
标题翻译：制造短沟道费米阈值场效应晶体管的方法，包括漏极场终止区
公开(公告)号：US5885876A
公开(公告)日：1999-03-23
申请号：US902150
申请日：1997-07-29
申请人： Michael W. Dennen
发明人： Michael W. Dennen
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L21/20 , H01L21/265
CPC分类号： H01L29/66651 , H01L29/1083 , H01L29/66575 , H01L29/7838
摘要： A Fermi-FET includes a drain field termination region between the source and drain regions, to reduce and preferably prevent injection of carriers from the source region into the channel as a result of drain bias. The drain field terminating region prevents excessive drain induced barrier lowering while still allowing low vertical field in the channel. The drain field terminating region is preferably embodied by a buried counterdoped layer between the source and drain regions, extending beneath the substrate surface from the source region to the drain region. The buried counterdoped layer may be formed using a three tub structure which produces three layers between the spaced apart source and drain regions. The drain field terminating region may also be used in a conventional MOSFET. The channel region is preferably formed by epitaxial deposition, so that the channel region need not be counterdoped relative to the drain field terminating region. Higher carrier mobility in the channel may thereby be obtained for a given doping level.
摘要翻译：费米FET包括在源极和漏极区之间的漏极场终止区，以减少并优选地防止由于漏极偏压而将载流子从源极区域注入到沟道中。漏极场终止区域防止过多的漏极引起的屏障降低，同时仍允许通道中的低垂直场。漏极端接区优选地由在源区和漏区之间的掩埋反掺杂层实现，在源极区到漏极区之下延伸到衬底表面下方。埋置的反掺杂层可以使用在隔开的源极和漏极区域之间产生三层的三层结构形成。漏极场终止区也可以用于传统的MOSFET。沟道区优选通过外延沉积形成，使得沟道区不需要相对于漏极场终止区被反掺杂。因此，对于给定的掺杂水平可以获得通道中较高的载流子迁移率。

37. 发明授权

US5525822A Fermi threshold field effect transistor including doping gradient regions 失效
标题翻译：费米阈值场效应晶体管包括掺杂梯度区域
公开(公告)号：US5525822A
公开(公告)日：1996-06-11
申请号：US431455
申请日：1995-05-01
申请人： Albert W. Vinal
发明人： Albert W. Vinal
IPC分类号： H01L21/265 , H01L29/10 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7838 , H01L21/26586 , H01L29/1087
摘要： A high saturation current, low leakage, Fermi threshold field effect transistor includes a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor. Source and drain doping gradient regions between the source/drain and the channel, respectively, of thickness greater than 300.ANG. are also provided. The threshold voltage of the Fermi-FET may also be lowered from twice the Fermi potential of the substrate, while still maintaining zero static electric field in the channel perpendicular to the substrate, by increasing the doping concentration of the channel from that which produces a threshold voltage of twice the Fermi potential. By maintaining a predetermined channel depth, preferably about 600.ANG., the saturation current and threshold voltage may be independently varied by increasing the source/drain doping concentration facing the channel and by increasing the excess carrier concentration in the channel, respectively. A Fermi-FET having a gate insulator thickness of less than 120.ANG., and a channel length of less than about 1 .mu.m can thereby provide a P-channel saturation current of at least 4 amperes per centimeter of channel width and an N-channel saturation current of at least 7 amperes per centimeter of channel width, with a leakage current of less than 10 picoamperes per micron of channel length using power supplies of between 0 and 5 volts.
摘要翻译：高饱和电流，低泄漏，费米阈值场效应晶体管包括面向通道的源极和漏极的预定最小掺杂浓度，以使晶体管的饱和电流最大化。还提供了源极/漏极和沟道之间的源极和漏极掺杂梯度区域，其厚度大于300。费米FET的阈值电压也可以从衬底的费米电位的两倍降低，同时通过垂直于衬底的通道仍保持零静态电场，通过增加沟道的掺杂浓度从产生阈值的掺杂浓度电压是费米电位的两倍。通过保持预定的沟道深度，优选约为600，饱和电流和阈值电压可以通过增加面向沟道的源极/漏极掺杂浓度并分别增加沟道中的过量载流子浓度来独立地变化。栅极绝缘体厚度小于120安培，且沟道长度小于约1μm的费米FET可以提供每通道宽度至少4安培的P沟道饱和电流和N沟道饱和电流每通道宽度至少为7安培，使用0至5伏特之间的电源，漏电流小于10微安/微米通道长度。

38. 发明授权

US5396457A Random access memory including or gate sensing networks 失效
标题翻译：随机存取存储器包括门检测网络
公开(公告)号：US5396457A
公开(公告)日：1995-03-07
申请号：US202531
申请日：1994-02-25
申请人： Albert W. Vinal
发明人： Albert W. Vinal
IPC分类号： G11C7/06 , G11C11/419 , G11C7/00
CPC分类号： G11C7/065 , G11C11/419
摘要： A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a and additional pull-up circuits to enhance high speed pair of symmetrical transfer function output inverters operation. The outputs of all of the differential latching inverters may be directly connected to a pair of OR gates with the output of one OR gate signifying that a logical ONE has been read and the output of the second OR gate signifying that a logical ZERO has been read. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may be internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers. A high speed, low power random access memory may thereby be provided.
摘要翻译：差分锁存逆变器使用具有偏斜电压传递函数的一对交叉耦合逆变器来快速地感测随机存取存储器中的一对位线上的差分信号，并且在读取操作期间提供高速感测。差分锁存逆变器还可以包括一个附加的上拉电路，以增强对称传输函数输出反相器操作的高速对。所有差分锁存逆变器的输出可以直接连接到一对或门，其中一个OR门的输出表示逻辑1已经被读取，并且第二OR门的输出表示已经读取了逻辑ZERO 。差分锁存逆变器可以用于具有主位线和信号位线的存储架构中，其中差分锁存逆变器连接到每对信号位线。主位线和信号位线在读取和写入操作期间彼此耦合，否则彼此分离。读和写操作可以在内部定时，而不需要响应于高速地址变化检测系统的外部时钟脉冲以及由延迟环段缓冲器产生的内部定时信号。因此可以提供高速，低功率随机存取存储器。

39. 发明授权

US5371396A Field effect transistor having polycrystalline silicon gate junction 失效
标题翻译：具有多晶硅栅极结的场效应晶体管
公开(公告)号：US5371396A
公开(公告)日：1994-12-06
申请号：US87509
申请日：1993-07-02
申请人： Albert W. Vinal , Michael W. Dennen
发明人： Albert W. Vinal , Michael W. Dennen
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L29/04 , H01L29/06
CPC分类号： H01L29/66575 , H01L21/28035 , H01L29/4916
摘要： A field effect transistor includes a polycrystalline silicon gate having a semiconductor junction therein. The semiconductor junction is formed of first and second oppositely doped polycrystalline silicon layers, and extends parallel to the substrate face. The polycrystalline silicon gate including the semiconductor junction therein is perfectly formed by implanting ions into the top of the polycrystalline silicon gate simultaneous with implantation of the source and drain regions. The semiconductor junction thus formed does not adversely impact the performance of the field effect transistor, and provides a low resistance ohmic gate contact. The gate need not be masked during source and drain implant, resulting in simplified fabrication.
摘要翻译：场效应晶体管包括其中具有半导体结的多晶硅栅极。半导体结由第一和第二相对掺杂的多晶硅层形成，并且平行于衬底面延伸。包括其中的半导体结的多晶硅栅极通过在注入源极和漏极区域的同时将离子注入到多晶硅栅极的顶部而完美地形成。这样形成的半导体结对场效应晶体管的性能没有不利影响，并且提供低电阻欧姆栅极接触。在源极和漏极注入期间，栅极不需要被掩模，从而简化了制造。

40. 发明授权

US5365483A Random access memory architecture including primary and signal bit lines and coupling means therefor 失效
标题翻译：随机存取存储器架构包括主要和信号位线及其耦合装置
公开(公告)号：US5365483A
公开(公告)日：1994-11-15
申请号：US201858
申请日：1994-02-25
申请人： Albert W. Vinal
发明人： Albert W. Vinal
IPC分类号： G11C7/06 , G11C11/419 , G11C7/00
CPC分类号： G11C7/065 , G11C11/419
摘要： A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may De internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers. A high speed, low power random access memory may thereby be provided.
摘要翻译：差分锁存逆变器使用具有偏斜电压传递函数的一对交叉耦合逆变器来快速地感测随机存取存储器中的一对位线上的差分信号，并且在读取操作期间提供高速感测。差分锁存逆变器还可以包括一对对称传递函数输出反相器和附加上拉电路，以增强高速度操作。差分锁存逆变器可以用于具有主位线和信号位线的存储架构中，其中差分锁存逆变器连接到每对信号位线。主位线和信号位线在读取和写入操作期间彼此耦合，否则彼此分离。读和写操作可以在内部定时，而不需要响应于高速地址变化检测系统的外部时钟脉冲，以及由延迟环段缓冲器产生的内部定时信号。因此可以提供高速，低功率随机存取存储器。

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