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    • 31. 发明申请
    • DEAD-TIME TRANSITION ADJUSTMENTS FOR SYNCHRONOUS POWER CONVERTERS
    • 同步电源转换器的死时间过渡调整
    • WO2009015205A1
    • 2009-01-29
    • PCT/US2008/070887
    • 2008-07-23
    • INTERSIL AMERICAS INC.DEQUINA, Noel B.
    • DEQUINA, Noel B.
    • H02M1/38H02M3/158H03K17/00
    • H02M3/158H02M1/38H03K17/165H03K17/6871H03K2217/0036
    • A method of operating a synchronous power converter detects when at least one of an upper power switch and a lower power switch of the converter transition to an off state during a dead-time transition interval between the upper power switch and the lower power switch. The method generates a first comparison signal, indicative of a voltage level at a phase node of the converter, in a dead-time adjustment circuit coupled to the converter. The method further detects a body diode conduction level of at least one of the upper and lower power switches in the off state using at least a second comparison signal generated in the dead-time adjustment circuit and adjusts the dead-time transition interval between the upper power switch and the lower power switch using at least one current source from the dead-time adjustment circuit to reduce the dead-time transition interval to a desired dead-time interval.
    • 操作同步功率转换器的方法检测在上电源开关和下电源开关之间的死区时间过渡间隔期间,转换器的上电源开关和下电源开关中的至少一个转换到断开状态。 该方法在耦合到转换器的死区时间调整电路中产生指示转换器的相位节点处的电压电平的第一比较信号。 该方法还使用在死区时间调整电路中产生的至少第二比较信号,检测处于断开状态的上下功率开关中的至少一个的体二极管导通电平,并且调节上限和下限功率开关之间的死区时间过渡间隔 电源开关和下电源开关,其使用来自死区时间调整电路的至少一个电流源,以将死区时间转换间隔减少到期望的死区间隔。
    • 34. 发明申请
    • MULTIPLE CHANNEL PROGRAMMABLE GAMMA CORRECTION VOLTAGE GENERATOR
    • 多通道可编程电位器校正电压发生器
    • WO2005048235A1
    • 2005-05-26
    • PCT/US2004/029878
    • 2004-09-10
    • INTERSIL AMERICAS INC.
    • YOUNGBLOOD, Douglas L.SMITH, Steven R.
    • G09G3/36
    • G09G3/3688G09G2310/027G09G2320/0247G09G2320/0276G09G2320/0606G09G2320/0673
    • A multiple channel programmable gamma correction voltage generator (200) including a resistor ladder (201), buffers (209), select logic SL1 - SLM, and a programmable non-volatile memory device (207). The memory provides select values indicative of one or more stored gamma correction values. The resistor ladder includes adjustable tap resistors distributed along the resistor ladder. The adjustable tap resistors provide multiple tap voltages distributed according to the gamma correction value. The buffers receive the tap voltages and provide gamma correction voltages. The select logic selects tap points of the adjustable tap resistors to select the tap voltages based on the select values stored in the memory. Additional resistors and switch logic may be included to enable re-positioning of the adjustable tap resistor within the resistor ladder. Latches (303) and address control may be provided on the memory to enable programming and selection of multiple gamma correction values.
    • 包括电阻梯(201),缓冲器(209),选择逻辑SL1-SLM和可编程非易失性存储器件(207)的多通道可编程伽玛校正电压发生器(200)。 存储器提供指示一个或多个存储的伽马校正值的选择值。 电阻梯包括沿电阻梯分布的可调节分接电阻器。 可调节抽头电阻提供根据伽马校正值分布的多个抽头电压。 缓冲器接收抽头电压并提供伽马校正电压。 选择逻辑选择可调节抽头电阻的抽头,根据存储在存储器中的选择值来选择抽头电压。 可以包括附加的电阻和开关逻辑,以使可调节抽头电阻器能够重新定位在电阻梯内。 可以在存储器上提供锁存器(303)和地址控制以使得能够编程和选择多个伽马校正值。
    • 36. 发明申请
    • LOW POWER, AREA-EFFICIENT CIRCUIT TO PROVIDE CLOCK SYNCHRONIZATION
    • 低功耗,提供时钟同步的区域电路
    • WO2004074991A2
    • 2004-09-02
    • PCT/US2004/003965
    • 2004-02-11
    • INTERSIL AMERICAS INC.DOYLE, Brent R.
    • DOYLE, Brent R.
    • G06F
    • H03K5/1534G06F1/08H03K5/19
    • A clock signal generator, which requires no clock selection pin includes a multiplexer to which external and internal clocks are applied. The external clock is further coupled directly and via an inverting delay to a logic circuit, the output of which controls a switching device connected across a capacitor. The capacitor is coupled to a current source and to a comparator that is coupled to a reference voltage. The comparator output serves as the select control for the multiplexer. The switching device repeatedly discharges the capacitor in response to the external clock signal, but otherwise allows the capacitor to be charged by the current source. The external clock signal is coupled to the output of the multiplexer, as long as the capacitor is repeatedly discharged by the external clock signal at a frequency sufficient to maintain the voltage across the capacitor less than the reference voltage.
    • 不需要时钟选择引脚的时钟信号发生器包括应用了外部和内部时钟的多路复用器。 外部时钟进一步直接耦合并通过反相延迟耦合到逻辑电路,逻辑电路的输出控制跨过电容器连接的开关器件。 电容器耦合到电流源和耦合到参考电压的比较器。 比较器输出用作多路复用器的选择控制。 开关器件响应于外部时钟信号重复地对电容器进行放电,但是另外允许电容器由电流源充电。 外部时钟信号耦合到多路复用器的输出端,只要电容器以足以使电容器两端的电压小于参考电压的频率由外部时钟信号反复放电。
    • 37. 发明申请
    • MULTIPHASE CONVERTER CONTROLLER USING SINGLE GAIN RESISTOR
    • 使用单增益电阻的多相变换器控制器
    • WO2004064236A1
    • 2004-07-29
    • PCT/US2003/037169
    • 2003-11-19
    • INTERSIL AMERICAS INC.
    • ISHAM, Robert, H.
    • H02M3/158
    • H02M3/1584H02M2001/0025
    • A controller for a multiphase converter including an error amplifier (211), a gain resistor RG, (311), a current sense circuit (301) and a gain adjust amplifier (305). The error amplifier generates an error signal ERR based on an error voltage developed across a feedback resistance RFB. The current sense circuit converts each of multiple sensed load currents into corresponding proportional voltages VS1 - VSN. The gain adjust amplifier circuit receives the proportional voltages and operates to apply at least one gain adjust voltage to the gain resistor to develop a gain adjust current that is applied through the feedback resistance to adjust gain. In one embodiment, the proportional voltages are time multiplexed (303) or averaged (401) to provide the gain adjust voltage(s). An IC (300, 400) integrating the multiphase converter need only include a single gain pin (309) for coupling to a gain resistor to set gain for each phase.
    • 一种用于多相转换器的控制器,包括误差放大器(211),增益电阻器RG,(311),电流检测电路(301)和增益调整放大器(305)。 误差放大器基于跨反馈电阻RFB产生的误差电压产生误差信号ERR。 电流检测电路将多个检测到的负载电流中的每一个转换成相应的比例电压VS1-VSN。 增益调节放大器电路接收比例电压并且操作以将至少一个增益调整电压施加到增益电阻器,以产生通过反馈电阻施加的增益调整电流以调节增益。 在一个实施例中,比例电压被时分复用(303)或平均化(401)以提供增益调整电压。 集成多相转换器的IC(300,400)仅需要包括用于耦合到增益电阻器以设置每相的增益的单个增益引脚(309)。
    • 40. 发明申请
    • WIRELESS RECEIVER FOR SORTING PACKETS USING CORRELATORS
    • 无线接收器,用于使用相关器分配包
    • WO2004017588A1
    • 2004-02-26
    • PCT/US2003/025980
    • 2003-08-19
    • INTERSIL AMERICAS INC.
    • HALFORD, Steven, D.FROGGE, Perry W.
    • H04L27/00
    • H04L27/0012H04L27/0008H04L27/2647
    • A wireless receiver (100) that sorts packets including a packet detector (105, 203), multiple correlators (107, 111), and multiple packet processors (109, 113). Each correlator correlates a received signal according to packet type. Each packet processor processes the received signal according to packet type. A signal power detector (105) may be provided to initially qualify the received signal as containing a packet, and the correlators determine whether a packet is present. The correlators may be configured for sequential or simultaneous correlation. For the simultaneous correlator configuration, a correlation monitor (203) is provided to monitor correlation results to determine if the received signal contains a packet, and if so, to determine packet type. A low SNR packet detector may be provided which correlates the received signal to detect weak packet signals. The signal power detector (105) may be omitted, and the correlators may simultaneously monitor the received signal while a correlation monitor may continuously monitor correlation results for packet detection.
    • 一种分组的无线接收机(100),包括分组检测器(105,203),多个相关器(107,111)和多个分组处理器(109,113)。 每个相关器根据分组类型将接收到的信号相关。 每个分组处理器根据分组类型处理接收到的信号。 可以提供信号功率检测器(105)以将接收到的信号初始限定为包含分组,并且相关器确定分组是否存在。 相关器可以被配置为顺序或同时相关。 对于同时相关器配置,提供相关监视器(203)以监视相关结果以确定接收到的信号是否包含分组,并且如果是,则确定分组类型。 可以提供低SNR分组检测器,其将接收的信号相关联以检测弱分组信号。 可以省略信号功率检测器(105),并且相关器可以同时监视接收到的信号,同时相关监视器可以连续监视分组检测的相关结果。