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31. 发明专利

JPH08250730A METHOD TO MANUFACTURE INTEGRATED CIRCUIT, METHOD TO DECREASE DIFFUSION OF P-TYPE DOPANT AND INTEGRATED CIRCUIT 失效
公开(公告)号：JPH08250730A
公开(公告)日：1996-09-27
申请号：JP26179595
申请日：1995-10-09
申请人： ADVANCED MICRO DEVICES INC
发明人： MOHAMETSUDO ANJIYUUMU , ARAN ERU SUTOYUUBAA , IBURAHIMU KEI BAAKI
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/08
摘要： PROBLEM TO BE SOLVED: To improve the performance of MOSFETs in N-MOS and P-MOS devices. SOLUTION: A MOS device is provided by using indium as a threshold value adjusting implantation material, which is implanted in a channel region 36 in an N-MOS device and/or a conductor gate 32, which is located on the region 36, is a P-MOS device. Indium ions are comparatively high in immobility, and the stability of the location of the MOS device is achieved at the regions of the region 36 and the gate 32, which are implanted with the indium ions. The indium ions are not easily segregated and diffused in the lateral direction and the direction vertical to a silicon substrate. For minimizing the problem of the skew of a threshold and an enhancement in the thickness of a gate oxide film, the immobility of the placement of the device is necessary. Moreover, it is believed that indium atoms in the region 36 minimize the effect of hot carries and problems related to the effect.

32. 发明专利

JPH08249085A MICROPROCESSOR, CLOCK CONTROL CIRCUIT FOR GIVING OF TIMING SIGNAL TO CONTROL INTERNAL CLOCK FREQUENCY OF MICROPROCESSOR AND METHOD FOR CONTROL OF FREQUENCY OF INTERNAL CLOCK SIGNAL TO DRIVE MICROPROCESSOR 失效
公开(公告)号：JPH08249085A
公开(公告)日：1996-09-27
申请号：JP25101995
申请日：1995-09-28
申请人： ADVANCED MICRO DEVICES INC
发明人： JIYOSEFU EI BEIRII
IPC分类号： G06F1/00 , G06F1/04 , G06F1/08 , G06F1/20
摘要： PROBLEM TO BE SOLVED: To provide a clock control circuit for controlling the frequency of the clock signals of a microprocessor. SOLUTION: This clock control circuit 101 controls the frequency of timing signals supplied to a clock generator and distribution unit 106 and the unit 106 supplies internal clock signals to the CPU core 102 of the microprocessor. A heat sensor 134 is integrated with a semiconductor die and the output signals are supplied to main and auxiliary temperature indicator units 130 and 132. The indicator units 130 and 132 respectively assert main and auxiliary indicator signals when the temperature of the die exceeds a main threshold value level and an auxiliary threshold value level. The main and auxiliary indicator units 130 and 132 are respectively related with hysteresis characteristics for which the main and auxiliary indicator signals are not de-asserted when they are asserted once until the temperature of the die becomes lower than prescribed first and second hysteresis points.

33. 发明专利

JPH08202563A COMPUTER SYSTEM 失效
公开(公告)号：JPH08202563A
公开(公告)日：1996-08-09
申请号：JP18678895
申请日：1995-07-24
申请人： ADVANCED MICRO DEVICES INC
发明人： DAGURASU DEII GEFUAATO , JIEIMUZU AARU MAKUDONARUDO , BIKUTAA EFU ANDOREIDO
IPC分类号： G06F11/22 , G06F9/48 , G06F11/14 , G06F9/46
摘要： PROBLEM TO BE SOLVED: To provide a computer system provided with an interruption driving system management mode for accessing a system management code. SOLUTION: A lock-out register is provided so as to evade access to the system management code while this computer system is operated in a normal mode. An interruption control unit 204 is connected to the ICE interruption line of a microprocessor core and a memory control unit 208 is controlled corresponding to the assertion of external 'debugging' interruption signals and external SMM interruption signals. During a normal operation, the microprocessor core executes a code from the 'normal' memory area of a system memory.

34. 发明专利

JPH08195089A APPARATUS AND METHOD FOR SIMULTANEOUS DETECTION OF PLURALITYOF CONDITIONS 失效
公开(公告)号：JPH08195089A
公开(公告)日：1996-07-30
申请号：JP16953095
申请日：1995-07-05
申请人： ADVANCED MICRO DEVICES INC
发明人： MAAKU SHIRA
IPC分类号： G11C15/04 , G06F12/08 , G06F12/12
摘要： PROBLEM TO BE SOLVED: To make it possible to simultaneously detect a plurality of conditions by sequentially outputting separate associativity, index to a specific Memory cell by the priority order of respective tasks. SOLUTION: An encoder 130 identifies the states of memory cells by each 8 of a group by the state bits of the respective cells. When any of inputs 134 to first block 132 exhibits specific memory cell condition such as data alteration of a memory cell storage, the block 132 outputs an altering signal 136a to a first level 2 function block 138. Further, an altering signal 140 is output to a level 3 function block 142. The blocks 142, 138 indicate that the high block of next order has alteration by signals 144, 137. Thus, the encoder 130 detects the memory cell state, and when the specific state such as alteration is detected simultaneously during observation of 8 memory cells, priority order can be set to the results.

35. 发明专利

JPH08194563A COMPUTER SYSTEM 失效
公开(公告)号：JPH08194563A
公开(公告)日：1996-07-30
申请号：JP17631795
申请日：1995-07-12
申请人： ADVANCED MICRO DEVICES INC
发明人： RITA EMU OBURAIEN
IPC分类号： G06F1/32 , G06F3/00
摘要： PROBLEM TO BE SOLVED: To reduce power consumption in a computer system by controlling a period after the generation of an address phase in a peripheral bus for which data from the peripheral bus are shielded inside a power management unit corresponding to a value inside a constitution register. SOLUTION: When a system monitor 204 detects a write cycle to an address required to be shielded inside the power management unit 202 corresponding to the value of the constitution register 209, a power management state machine 206 latches the data from a peripheral connection interface(PCI) bus 220 to the system monitor 204 in a PCI clock cycle following immediately after an address cycle or after one, two or three clock cycles. During the data phase of the PCI cycle, the byte enable signals of the PCI bus 220 are decoded by the system monitor 204 further and a specified byte to be shielded is decided inside the constitution register 209.

36. 发明专利

JP2517357B2 失效
公开(公告)号：JP2517357B2
公开(公告)日：1996-07-24
申请号：JP9803888
申请日：1988-04-20
申请人： ADVANCED MICRO DEVICES INC
发明人： UIRIAMU EICHI AANORUDO ZA SAADO , MOHAMADO FUAANAAMU , JATSUKU SURIWA
IPC分类号： H01L21/027 , G03C5/00 , G03F1/00 , G03F1/14 , G03F7/09 , G03F7/11 , G03F7/26 , H01L21/30

37. 发明专利

JPH08180013A COMPUTER SYSTEM,METHOD FOR RECONFIGURATION OF CONFIGURATION REGISTER OF PCI BUS DEVICE IN RESPONSE TO CHANGE IN PCI BUS CLOCK SIGNAL FREQUENCY AND METHOD IN WHICH PCI BUS INTERFACENOTIFIES OPERATOR OF OPERATING SPEED DIFFERENT FROM PCI BUS 失效
公开(公告)号：JPH08180013A
公开(公告)日：1996-07-12
申请号：JP23382795
申请日：1995-09-12
申请人： ADVANCED MICRO DEVICES INC
发明人： SHIYAAMAN RII , MAIKERU TEII WAIZAA
IPC分类号： G06F13/36 , G06F1/08 , G06F13/42
摘要： PROBLEM TO BE SOLVED: To provide a system for promoting the operation at a higher clock frequency of a peripheral bus such as a PCI bus. SOLUTION: An enable line (66MHzENABLE) is connected to respective devices 70 and 80 present on the PCI bus 100. When all the devices can perform a high frequency operation (66MHz, for instance,) the enable line is pulled up through a pull-up register 62. For the device incapable of the high frequency operation, at the time of corresponding to specifications in an industrial field at present, the enable line is connected to the ground in the inside. Thus, the enable line is asserted in the case that all the PCI devices 70 and 80 support the high frequency operation but it is de-asserted otherwise. An exclusive state bit for making the system alarm non-matching between the device and bus ability can be provided and a configuration register can be automatically reconstituted when the parameter of the system is changed.

38. 发明专利

JPH08179928A APPARATUS AND METHOD FOR DECISION OF NUMBER OF PRECEDING COUNTING PLACES IN DATA INPUT SIGNAL AS WELL AS COMPUTER SYSTEM 失效
公开(公告)号：JPH08179928A
公开(公告)日：1996-07-12
申请号：JP21344195
申请日：1995-08-22
申请人： ADVANCED MICRO DEVICES INC
发明人： RIOONERU ROUZAANO
IPC分类号： G06F7/00 , G06F7/74
摘要： PROBLEM TO BE SOLVED: To provide a device and a method for deciding the number of digits preceding a specified digit in data input signals. SOLUTION: The digits of the data input signals provided with X groups composed of R+M digits are divided so as to make X different first counter detectors 201 receive the M digits and to make second counter detectors 216 receive the R digits. A counter detector decides the number of most significant count digit preceding a most significant non-count digit and detects the presence of a non-count digit. A decoder 220 receives the output of the first counters 201 and reports the number of corresponding counts to a connector 222 in response to the detection of the non-count digit in a highest order group composed of the M digits provided with the non-count digit. A third counter detector 218 decides and reports the number of the most significant groups composed of the M digits provided with the non-count digit. The output of the third counter detector 218 is connected with the output of the decoder 220 and the connection indicates the number of the preceding count digits.

39. 发明专利

JPH08179846A COMPUTER SYSTEM AND METHOD FOR ADJUSTMENT OF FREQUENCY OF CPU CLOCK SIGNAL AT INSIDE OF COMPUTER SYSTEM 失效
公开(公告)号：JPH08179846A
公开(公告)日：1996-07-12
申请号：JP22501395
申请日：1995-09-01
申请人： ADVANCED MICRO DEVICES INC
发明人： RUPAKA MAHARINGAIA , TERII HARETSUTO
IPC分类号： G06F15/78 , G06F1/04 , G06F1/20
摘要： PROBLEM TO BE SOLVED: To provide a computer system provided with a heuristic clock speed optimization mechanism for making the computer system capable of performing an operation at an optimum clock frequency without being overheated. SOLUTION: A microprocessor 102 is provided with a programmable heat sensor 130 incorporated on a relating semiconductor die for generating signals for indicating the temperature of the semiconductor die. Control signals are supplied to a frequency synthesizer 110 for controlling the frequency of CPU clock signals. The frequency synthesizer 110 is dynamically controlled so as to change the frequency of the CPU clock signals so as to make the microprocessor 102 perform the operation at the optimum frequency while preventing overheating.

40. 发明专利

JPH08129477A SYSTEM AND APPARATUS FOR MANAGEMENT OF DATA OF COMPUTER PERIPHERAL EQUIPMENT 失效
公开(公告)号：JPH08129477A
公开(公告)日：1996-05-21
申请号：JP12385595
申请日：1995-05-23
申请人： ADVANCED MICRO DEVICES INC
发明人： RICHIYAADO EI RERUFU
IPC分类号： B41J29/38 , B41J5/30 , G06F5/00 , G06F12/02
摘要： PURPOSE: To provide a system and a method for managing digital data on a computer peripheral equipment with data received from a host computer. CONSTITUTION: The system contains a processing circuit for receiving data from the host 109 and controlling the computer peripheral equipment by using data. The system contains a memory device 17 for storing data and containing plural storage places. The system also contains a memory management unit 16 for controlling the storage of data in the memory device. The system contains a compression program for compressing/storing data in the memory. The memory management unit 16 decides a time when the quantity of data stored in the memory device exceeds a previously decided threshold and generates a compression signal. The compression program responds to the compression signal by compressing and storing data.

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