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32. 发明专利

JP4846889B2 Manufacturing method for an integrated circuit 有权
公开(公告)号：JP4846889B2
公开(公告)日：2011-12-28
申请号：JP33420599
申请日：1999-11-25
申请人：エスティーマイクロエレクトロニクスエス.アール.エル.STMicroelectronics S.r.l.
发明人：マウレッリアルフォンソ , ジュセッペカッペレッティパオロ
IPC分类号： H01L27/115 , H01L21/8238 , H01L21/8247 , H01L27/092 , H01L27/105 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546 , Y10S438/981
摘要： A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate (1), forming a first gate oxide layer (3) for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate (1), forming a second gate oxide layer (5) for memory cells of the memory device; on the first and second gate oxide layers (3,5), forming from a first polysilicon layer (6) gate electrodes (8,9) for the first transistors, and floating-gate electrodes (7) for the memory cells; forming over the floating-gate electrodes (7) of the memory cells a dielectric layer (18); on third portions of the semiconductor substrate (1), forming a third gate oxide layer (24) for second transistors operating at the low operating voltage; on the dielectric layer (18) and on the third portions of the semiconductor substrate (1), forming from a second polysilicon layer (25) control gate electrodes (29) for the memory cells, and gate electrodes (26,27) for the second transistors; in the first portions of the semiconductor substrate (1), forming source and drain regions (12,13;16,17) for the first transistors; in the second portions of the semiconductor substrate (1), forming source and drain regions (30,31) for the memory cells; in the third portions of the semiconductor substrate (1), forming source and drain regions for the second transistors.

33. 发明专利

JP4820058B2 Micro fuel cell and related methods comprising an anode and a cathode microfluidic channel 有权
公开(公告)号：JP4820058B2
公开(公告)日：2011-11-24
申请号：JP2004013433
申请日：2004-01-21
申请人：エスティーマイクロエレクトロニクスエス.アール.エル.STMicroelectronics S.r.l. , エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics,Inc
发明人：マストマッテオウバルド , ロプリオールステファノ , パルミエリミシェル
IPC分类号： H01M8/02 , H01M4/86 , H01M4/88 , H01M4/94 , H01M8/00 , H01M8/10 , H01M8/14 , H01M8/24
CPC分类号： H01M8/241 , H01M4/8626 , H01M8/0247 , H01M8/1007 , Y02P70/56
摘要： A microfuel cell includes a substrate and a plurality of spaced-apart PEM dividers extending outwardly to define anodic and cathodic microfluidic channels. An anodic catalyst/electrode lines at least a portion of the anodic microfluidic channels, and a cathodic catalyst/electrode lines at least a portion of the cathodic microfluidic channels. Each anodic and cathodic catalyst/electrode may extend beneath an adjacent portion of a PEM divider in some embodiments. Alternately, the microfuel cell may include a plurality of stacked substrates, in which a first substrate has first microfluidic fuel cell reactant channels. A PEM layer may be adjacent the first surface of the first substrate, an anodic catalyst/electrode layer may be adjacent one side of the PEM layer, and a cathodic catalyst/electrode layer may be adjacent an opposite side of the PEM layer. An adhesive layer may secure the first substrate to an adjacent substrate defining at least a second microfluidic fuel cell reactant channel.

34. 发明专利

JP2011083186A Device for controlling resonant converter 审中-公开
标题翻译：用于控制谐振转换器的装置
公开(公告)号：JP2011083186A
公开(公告)日：2011-04-21
申请号：JP2010229173
申请日：2010-10-11
申请人： Stmicroelectronics Srl , エスティーマイクロエレクトロニクスエス.アール.エル.STMicroelectronics S.r.l.
发明人： ADRAGNA CLAUDIO
IPC分类号： H02M3/28
CPC分类号： H02M3/3376 , H02M1/08 , H02M2001/0058 , Y02B70/1433 , Y02B70/1491
摘要： PROBLEM TO BE SOLVED: To provide a switching circuit control device for a resonant converter that has a DC current output. SOLUTION: A half-bridge consisting of a first transistor Q1 and a second transistor Q2 generates a cyclic square wave voltage for driving a resonant circuit 300 for a resonant converter. A control device 100 has a circuit means 101 adapted to control the half-bridge according to a charging or discharging time period of a capacitor Ct and to synchronize the start time Tstart of a discharging or charging time period of the capacitor Ct that crosses a zero value of the signal Vs representing the current Is flowing in the resonant circuit 300; and additional means 102 and 103 adapted to control switching-off of the first transistor Q1 or the second transistor Q2 at the end of the discharging or charging time period of the capacitor Ct. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有直流电流输出的谐振转换器的开关电路控制装置。解决方案：由第一晶体管Q1和第二晶体管Q2组成的半桥产生用于驱动用于谐振转换器的谐振电路300的循环方波电压。控制装置100具有电路装置101，其适于根据电容器Ct的充电或放电时间段来控制半桥，并且使电容器Ct的放电或充电时间段的开始时间Tstart同步为零表示在谐振电路300中流过的电流Is的信号Vs的值; 以及适于在电容器Ct的放电或充电时间段结束时控制第一晶体管Q1或第二晶体管Q2的截止的附加装置102和103。版权所有（C）2011，JPO＆INPIT

35. 发明专利

JP4623775B2 Vdmos transistor 有权
公开(公告)号：JP4623775B2
公开(公告)日：2011-02-02
申请号：JP1337099
申请日：1999-01-21
申请人：エスティーマイクロエレクトロニクスエス.アール.エル.STMicroelectronics S.r.l.
发明人：アントニオアンドレイニ , ジョルジオキオッツィ
IPC分类号： H01L27/04 , H01L29/06 , H01L21/76 , H01L21/822 , H01L27/02 , H01L27/06 , H01L29/739 , H01L29/78
CPC分类号： H01L27/0251 , H01L29/0619 , H01L29/7809 , H01L29/7811

37. 发明专利

JP2010167272A Process for manufacturing integrated membrane of nozzles in mems technology for spray device and spray device using the integrated membrane 审中-公开
标题翻译：用于喷涂装置的MEMS技术中的喷嘴的集成膜和使用集成膜的喷射装置的方法
公开(公告)号：JP2010167272A
公开(公告)日：2010-08-05
申请号：JP2009290875
申请日：2009-12-22
申请人： Stmicroelectronics Srl , エスティーマイクロエレクトロニクスエス.アール.エル.STMicroelectronics S.r.l.
发明人： MERASSI ANGELO ANTONIO , PESCI ANGELO , VIGNA BENEDETTO , GALEAZZI ERNESTINO , MANTOVANI MARCO
IPC分类号： A61M11/00 , H01L21/3065
CPC分类号： A61M15/009 , B05B1/14 , B05B17/0638 , B05D7/00 , B81B2201/058 , B81B2203/0127 , B81C1/00087 , Y10T29/49401
摘要： PROBLEM TO BE SOLVED: To provide a process for manufacturing integrated membrane of nozzles in MEMS technology and a spray device including the membrane without defects of conventional technology.
SOLUTION: The process for manufacturing a membrane of nozzles of a spray device, comprises the steps of laying a substrate (11), forming a membrane layer (13) on the substrate (11), forming a plurality of nozzles (14) in the membrane layer (13), forming a plurality of supply channels (15) in the substrate (11), each supply channel (15) being substantially aligned in a vertical direction to a respective nozzle of the plurality of nozzles (14) and directly communicating with the respective nozzle (14).
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于制造MEMS技术中的喷嘴的集成膜的方法和包括膜的喷射装置，而没有常规技术的缺陷。解决方案：用于制造喷雾装置的喷嘴膜的方法包括以下步骤：在基材（11）上铺设基材（11），形成膜层（13），形成多个喷嘴（14））在所述膜层（13）中形成，在所述基板（11）中形成多个供给通道（15），每个供应通道（15）在与所述多个喷嘴（14）中的相应喷嘴的垂直方向上基本对准，并且与相应的喷嘴（14）直接连通。版权所有（C）2010，JPO＆INPIT

39. 发明专利

JP4330057B2 Flash compatible eeprom 有权
公开(公告)号：JP4330057B2
公开(公告)日：2009-09-09
申请号：JP2000186781
申请日：2000-06-21
申请人：エスティーマイクロエレクトロニクスエス.アール.エル.STMicroelectronics S.r.l.
发明人：カッペレッティパオロ
IPC分类号： G11C16/02 , G11C11/00 , G11C16/16 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/16 , G11C11/005 , G11C16/34
摘要： A flash compatible EEPROM device has a first flash matrix and a second matrix with EEPROM functionalities of substantially similar layout, both are divided into blocks of cells formed in substrate regions isolated from one another. In said second matrix, the information is organized in pages each one contained in a row of memory cells of one of said block of subdivision of the matrix. A hierarchic structure including a row decoder addresses the wordline of all the cells of a selected row of the block, co-operating with a column decoder in selecting single cells of the rows. A boosted voltage of polarity opposite to the single supply voltage of the device is applied during an erasing phase to a single wordline selected by means of said row decoder, to page-erase said information by applying a boosted voltage to the common source of all the cells of the block and to the isolated region of the substrate containing all the cells of the block. A logical circuit confirms the programmed state of each cell containing a logic zero information of the not erased rows of the block after one or more rows or pages have been erased, applying said first boosted voltage to a wordline at a time and said supply voltage to one or more bitlines at a time for confirming a preexistent programmed state, while keeping to ground voltage the common source of all the cells of the block and the confined isolated region of the substrate.

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