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21. 发明专利

JP2661368B2 失效
公开(公告)号：JP2661368B2
公开(公告)日：1997-10-08
申请号：JP50003093
申请日：1992-04-17
申请人： MOTOROORA INC
发明人： DEIRON TOOMASU EMU , KUROROTSUPU ROBAATO KEE , METOROKA MAIKERU PII
IPC分类号： G06F11/14 , G06F11/08 , G06F11/18 , G06F13/00 , H03M13/43 , H04L1/08 , H04L1/16 , H04L1/18
摘要： The process of the present invention error corrects sub-audible data words that have been transmitted over a voice channel. A data word may be transmitted up to three times if an acknowledge is not received by the transmitter. If any of the three possible repeats of the received data word are decodable, an acknowledgment is transmitted. If all three repeats of the data word contain uncorrectable errors, a bitwise majority vote is performed on the three data words. If the result of the majority vote is decodable, an acknowledgement is transmitted to the sender.

22. 发明专利

JPH0211184B2 失效
公开(公告)号：JPH0211184B2
公开(公告)日：1990-03-13
申请号：JP5400283
申请日：1983-03-31
申请人： JAPAN BROADCASTING CORP
发明人： YAMADA TSUKASA
IPC分类号： H03M13/00 , H03M13/43

23. 发明专利

JPS61131270A Block address correcting circuit 失效
标题翻译：块地址纠正电路
公开(公告)号：JPS61131270A
公开(公告)日：1986-06-18
申请号：JP25346384
申请日：1984-11-30
申请人： Sony Corp
发明人： YAMAMOTO YOSHIKAZU
IPC分类号： G11B20/12 , H03M13/27 , H03M13/43
CPC分类号： H03M13/43
摘要： PURPOSE:To make a block address correction stronger by obtaining a majority of a difference signal between an output of a counter and a block address in the input data by a reference block signal and calculating a block address from the decision output. CONSTITUTION:Since a block address code added to a block each has a continuity, the difference between an output of a counter 13 counted up by a reference block signal and a block address in input data DIN is to be a constant value. The difference is obtained by a subtracter circuit 12 and the difference of a block address, to which influences of transmission errors are given, will not be able to go to a prescribed value. Then, by a majority logic circuit 16, the majority of a difference signal which is continuous, for example, concerning five blocks, is obtained, a correct difference is determined. The output of a counter 20 counted up by a block signal to the determining difference is added by an adder circuit 19 and the value of a block address is calculated. Consequently, even when error correcting code processing is not executed to a block address code, the block address can be sufficiently corrected.
摘要翻译：目的：通过参考块信号获得计数器的输出和输入数据中的块地址之间的大部分差分信号，并从判定输出计算块地址，使块地址校正更强。构成：由于添加到块的块地址码各自具有连续性，所以通过参考块信号计数的计数器13的输出与输入数据DIN中的块地址之间的差异是恒定值。该差异由减法电路12获得，并且给出了传输误差影响的块地址的差异将不能达到规定值。然后，通过多数逻辑电路16，获得例如关于五个块的连续的差分信号的大部分，确定正确的差异。计数器20的输出通过块信号计数到确定差值，由加法器电路19相加，并且计算块地址的值。因此，即使不对块地址码执行纠错码处理，也可以充分校正块地址。

24. 发明专利

JP6188867B2 パケットを復元するための方法及びシステム有权
公开(公告)号：JP6188867B2
公开(公告)日：2017-08-30
申请号：JP2016100971
申请日：2016-05-20
申请人：株式会社日立製作所
发明人：リテッシュクマールカッレ
IPC分类号： H04L12/951 , H03M13/43 , H04L1/08
CPC分类号： H04L1/0045 , G06F11/1004 , H04L1/0061 , H04L1/08 , H04B1/38 , H04L69/324

25. 发明专利

JP2012198586A Error correction circuit, memory device, and error correction method 有权
标题翻译：错误校正电路，存储器件和错误校正方法
公开(公告)号：JP2012198586A
公开(公告)日：2012-10-18
申请号：JP2011060500
申请日：2011-03-18
申请人： Fujitsu Telecom Networks Ltd , 富士通テレコムネットワークス株式会社
发明人： KONDO RYUICHI
IPC分类号： G06F12/16 , H03M13/43
CPC分类号： Y02D10/13
摘要： PROBLEM TO BE SOLVED: To provide an error correction circuit, a memory device, and an error correction method which can perform error correction at high-speed and suppress an increase in structure and/or power consumption of the error correction circuit.SOLUTION: An error correction circuit comprises: input means 153 for inputting an odd number of pieces of redundant binary information in current values; conversion means 151 for converting the sum of the odd number of current values input via the input means into voltage; and first determination means 152 for outputting binary information according to whether the voltage output by the conversion means is equal to or more than a first preset threshold.
摘要翻译：解决的问题：提供可以高速执行纠错并且抑制纠错电路的结构和/或功耗的增加的纠错电路，存储装置和纠错方法。解决方案：纠错电路包括：输入装置153，用于输入当前值中奇数个冗余二进制信息; 转换装置151，用于将通过输入装置输入的奇数个电流值的和转换为电压; 以及用于根据转换装置输出的电压是否等于或大于第一预设阈值来输出二进制信息的第一确定装置152。版权所有（C）2013，JPO＆INPIT

26. 发明专利

JP4454890B2 Decoding circuit and a communication device 有权
公开(公告)号：JP4454890B2
公开(公告)日：2010-04-21
申请号：JP2001203652
申请日：2001-07-04
申请人：株式会社東芝
发明人：芳浩丹野 , 浩嗣小倉
IPC分类号： H03M7/38 , H03M13/43 , H03M13/45 , H04B3/06 , H04J13/00 , H04L1/08

27. 发明专利

JP3790190B2 Digital transmission system 有权
公开(公告)号：JP3790190B2
公开(公告)日：2006-06-28
申请号：JP2002186634
申请日：2002-06-26
申请人：日本電信電話株式会社
发明人：宮本　　裕 , 将人富沢 , 章平野 , 由明木坂
IPC分类号： H03M13/43 , H04B10/2507 , H04B10/556 , H04L25/06
CPC分类号： H04L25/062

28. 发明专利

JP2004527149A Apparatus for generating and code words to generate code words 审中-公开
公开(公告)号：JP2004527149A
公开(公告)日：2004-09-02
申请号：JP2002552197
申请日：2001-12-04
申请人：ユービネティクスリミティド
发明人：クック，ポール
IPC分类号： H03M7/04 , H03M13/15 , H03M13/43 , H03M13/45 , H03M13/47 , H04L1/00
CPC分类号： H03M13/45 , H03M13/136
摘要：第１次リードマラーコードを使って符号化されるデータ語が、高速アダマール変換（ＦＨＴ）を使って復号化される。データ語が一つの端部において不使用ビットの数を有することが知られている場合は、コード語の軟判定が順序変換される。複数群の軟判定について多数決投票を行い、一連の軟判定を生成し、新たなコード語を形成する。新コード語は、最初に受信されたコード語に提供されるＦＨＴより低次のＦＨＴを使って、復号化される。

29. 发明专利

JP2003348064A Communication system, receiver and communication method 有权
标题翻译：通信系统，接收机和通信方法
公开(公告)号：JP2003348064A
公开(公告)日：2003-12-05
申请号：JP2002149174
申请日：2002-05-23
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MATSUMOTO WATARU
IPC分类号： H03M13/19 , H03M13/11 , H03M13/33 , H03M13/37 , H03M13/39 , H03M13/43 , H03M13/45 , H04L1/00 , H04L7/02 , H04L7/033 , H04L7/08 , H04L27/00
CPC分类号： H04L27/0014 , H03M13/1102 , H03M13/336 , H04L1/0041 , H04L1/005 , H04L1/0057 , H04L1/0063 , H04L7/0062 , H04L2027/003 , H04L2027/0053 , H04L2027/0067
摘要： PROBLEM TO BE SOLVED: To obtain a receiver for precisely controlling synchronization without using a preamble and a user code. SOLUTION: The receiver is provided with a decryption part 5 for executing a single LDPC (low density parity check) decryption by 'sum-product algorithm' for a received signal at a plurality of sample points to be candidates for a sample starting point, a phase error estimation part 6 for executing estimation of a phase error by MMSE (minimum means squared error) by using soft decision information to be outputted in processes of the decryption, a multiplier 4 for compensating the received signal on the basis of an estimation result and a frame decision part 7 for deciding whether or not compensation processing is terminated by comparing an average (A) of absolute values of the latest logarithmic likelihood ratio with an average (B) of absolute values of logarithmic likelihood ratio just preceding the latest one, terminating the compensation processing in the case of B≥A and after that, defining a point corresponding to the maximum value of the averages of the logarithmic likelihood ratio in the candidates for the sample starting point as a sample starting point of a frame. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：获得用于在不使用前同步码和用户代码的情况下精确地控制同步的接收机。解决方案：接收机设置有解密部分5，用于对多个采样点处的接收信号执行“和积算法”的单个LDPC（低密度奇偶校验）解密，作为样本开始的候选点，用于通过使用在解密的处理中输出的软判决信息来通过MMSE（最小均方误差）来执行相位误差的估计的相位误差估计部分6，用于基于解密来补偿接收信号的乘法器4 估计结果和帧决定部分7，用于通过将最新对数似然比的绝对值的平均值（A）与刚刚在最新对数似然比之前的对数似然比的绝对值的平均值（B）进行比较来判定是否终止补偿处理）在B≥A的情况下终止补偿处理，然后定义对应于对数似然度的平均值的最大值的点作为采样起始点的候选者的比例作为帧的采样起始点。版权所有（C）2004，JPO

30. 发明专利

JP2003264467A VITERBI DECODING CIRCUIT 审中-公开
公开(公告)号：JP2003264467A
公开(公告)日：2003-09-19
申请号：JP2002063480
申请日：2002-03-08
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NAGANO KOICHI
IPC分类号： G06F11/10 , H03M13/23 , H03M13/41 , H03M13/43 , H04L1/00
摘要： PROBLEM TO BE SOLVED: To enhance performance of a viterbi decoding circuit while suppressing increase of the circuit scale in the viterbi decoding circuit. SOLUTION: A path storage circuit 20A holds the surviving path and is provided with a plurality of stages of path holding parts 31, 32,..., 3n, each of the stages corresponding to its time. A majority decision judging circuit 5 judges majority decision by defining, as the input, the output values of three delaying units including delaying units of the highest rank and the lowest rank that define the selected output of a selection circuit 4 as the input among six delay units held by the path holding part 3n of the last stage. COPYRIGHT: (C)2003,JPO

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