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21. 发明专利

JP3384347B2 Error compensation method, and error compensation device using a method 有权
公开(公告)号：JP3384347B2
公开(公告)日：2003-03-10
申请号：JP1209199
申请日：1999-01-20
申请人：日本電信電話株式会社
发明人：厚太田 , 伸晃望月 , 洋一松本 , 正弘梅比良
IPC分类号： H04L1/14 , H03M13/43 , H04L1/18 , H04L12/70 , H04L12/56

22. 发明专利

JP2002314434A METHOD, DEVICE AND PROGRAM FOR LEARNING CORRELATION MATRIX 失效
公开(公告)号：JP2002314434A
公开(公告)日：2002-10-25
申请号：JP2001119614
申请日：2001-04-18
申请人： NEC CORP
发明人： MITSUYA NAOKI
IPC分类号： G06F11/10 , G06F17/15 , G06F17/16 , H03M13/39 , H03M13/43
摘要： PROBLEM TO BE SOLVED: To provide a method for learning a correlation matrix, which obtains an optimum correlation matrix at an optimum threshold to ensure a sufficient margin against bit errors among all code words by stepwise increasing the threshold at learning of the correlation matrix as the learning progresses. SOLUTION: An arithmetic section 15 obtains a product of a code word X and a correlation matrix W. A comparison section 17 compares the product from an respectively section with a threshold ±TH. A learning supervisory section 18 updates the correlation matrix on the basis of the result of comparison by the comparison section. After updating all the code words, when the result of the arithmetic operation using the correlation matrix after the update is within a prescribed range, the threshold is revised and the learning of all the code words is again repeated. Furthermore, when the arithmetic result using the correlation matrix after the update is not within a prescribed range and the arithmetic result before the update is equal to the arithmetic result after the update, the update value of the correlation matrix is decreased and the learning is repeated. When the update value of the correlation matrix is zero, it is considered that an optimum threshold and an optimum correlation matrix are obtained and the learning is completed.

23. 发明专利

JP2002534902A 失效
公开(公告)号：JP2002534902A
公开(公告)日：2002-10-15
申请号：JP2000592975
申请日：1999-12-30
IPC分类号： H04B7/24 , H03M13/29 , H03M13/41 , H03M13/43 , H03M13/45 , H04L1/00

24. 发明专利

JP2002084201A MAXIMUM LIKELIHOOD CODE RETRIEVAL DEVICE AND METHOD 失效
公开(公告)号：JP2002084201A
公开(公告)日：2002-03-22
申请号：JP2001183456
申请日：2001-06-18
申请人： KIKAI GAKUSHU KENKYUSHO KK
发明人： SHIMADA MICHIO , SUZUKI HISASHI
IPC分类号： G06F11/10 , H03M13/39 , H03M13/43
摘要： PROBLEM TO BE SOLVED: To provide a maximum likelihood code retrieval device used for an error correction decoder that can retrieve a maximum likelihood code at a high-speed. SOLUTION: The maximum likelihood code retrieval device is provided with comparison means (captions 12 in Figure 1) that receive numerals denoting respective likelihood values of symbol sequences and one threshold and compares the threshold with each of the numerals representing the respective likelihood values, a count means (caption 13 in Figure 1) that discriminates to which of 0, 1, or 2 or more the number of comparison results denoting that the numerals representing the likelihood values is equal to the threshold value or over among the comparison results outputted from a plurality of the comparison means corresponds and provides an output of the discrimination result, a selection means (caption 14 in Figure 1) that selects and outputs a symbol sequence corresponding to any of the comparison means whose comparison result indicates one when one of the comparison means depicts that the numeral indicating the likelihood is the threshold or more, and a control means (caption 11 in Figure 1) that increases/decreases the threshold value on the basis of the discrimination result outputted from the count means and supplies the threshold to the comparison means, and the selection means provides an output externally.

25. 发明专利

JP2661368B2 失效
公开(公告)号：JP2661368B2
公开(公告)日：1997-10-08
申请号：JP50003093
申请日：1992-04-17
申请人： MOTOROORA INC
发明人： DEIRON TOOMASU EMU , KUROROTSUPU ROBAATO KEE , METOROKA MAIKERU PII
IPC分类号： G06F11/14 , G06F11/08 , G06F11/18 , G06F13/00 , H03M13/43 , H04L1/08 , H04L1/16 , H04L1/18
摘要： The process of the present invention error corrects sub-audible data words that have been transmitted over a voice channel. A data word may be transmitted up to three times if an acknowledge is not received by the transmitter. If any of the three possible repeats of the received data word are decodable, an acknowledgment is transmitted. If all three repeats of the data word contain uncorrectable errors, a bitwise majority vote is performed on the three data words. If the result of the majority vote is decodable, an acknowledgement is transmitted to the sender.

26. 发明专利

JPH0211184B2 失效
公开(公告)号：JPH0211184B2
公开(公告)日：1990-03-13
申请号：JP5400283
申请日：1983-03-31
申请人： JAPAN BROADCASTING CORP
发明人： YAMADA TSUKASA
IPC分类号： H03M13/00 , H03M13/43

27. 发明专利

JPS61131270A Block address correcting circuit 失效
标题翻译：块地址纠正电路
公开(公告)号：JPS61131270A
公开(公告)日：1986-06-18
申请号：JP25346384
申请日：1984-11-30
申请人： Sony Corp
发明人： YAMAMOTO YOSHIKAZU
IPC分类号： G11B20/12 , H03M13/27 , H03M13/43
CPC分类号： H03M13/43
摘要： PURPOSE:To make a block address correction stronger by obtaining a majority of a difference signal between an output of a counter and a block address in the input data by a reference block signal and calculating a block address from the decision output. CONSTITUTION:Since a block address code added to a block each has a continuity, the difference between an output of a counter 13 counted up by a reference block signal and a block address in input data DIN is to be a constant value. The difference is obtained by a subtracter circuit 12 and the difference of a block address, to which influences of transmission errors are given, will not be able to go to a prescribed value. Then, by a majority logic circuit 16, the majority of a difference signal which is continuous, for example, concerning five blocks, is obtained, a correct difference is determined. The output of a counter 20 counted up by a block signal to the determining difference is added by an adder circuit 19 and the value of a block address is calculated. Consequently, even when error correcting code processing is not executed to a block address code, the block address can be sufficiently corrected.
摘要翻译：目的：通过参考块信号获得计数器的输出和输入数据中的块地址之间的大部分差分信号，并从判定输出计算块地址，使块地址校正更强。构成：由于添加到块的块地址码各自具有连续性，所以通过参考块信号计数的计数器13的输出与输入数据DIN中的块地址之间的差异是恒定值。该差异由减法电路12获得，并且给出了传输误差影响的块地址的差异将不能达到规定值。然后，通过多数逻辑电路16，获得例如关于五个块的连续的差分信号的大部分，确定正确的差异。计数器20的输出通过块信号计数到确定差值，由加法器电路19相加，并且计算块地址的值。因此，即使不对块地址码执行纠错码处理，也可以充分校正块地址。

28. 发明专利

JP6188867B2 パケットを復元するための方法及びシステム有权
公开(公告)号：JP6188867B2
公开(公告)日：2017-08-30
申请号：JP2016100971
申请日：2016-05-20
申请人：株式会社日立製作所
发明人：リテッシュクマールカッレ
IPC分类号： H04L12/951 , H03M13/43 , H04L1/08
CPC分类号： H04L1/0045 , G06F11/1004 , H04L1/0061 , H04L1/08 , H04B1/38 , H04L69/324

29. 发明专利

JP2012198586A Error correction circuit, memory device, and error correction method 有权
标题翻译：错误校正电路，存储器件和错误校正方法
公开(公告)号：JP2012198586A
公开(公告)日：2012-10-18
申请号：JP2011060500
申请日：2011-03-18
申请人： Fujitsu Telecom Networks Ltd , 富士通テレコムネットワークス株式会社
发明人： KONDO RYUICHI
IPC分类号： G06F12/16 , H03M13/43
CPC分类号： Y02D10/13
摘要： PROBLEM TO BE SOLVED: To provide an error correction circuit, a memory device, and an error correction method which can perform error correction at high-speed and suppress an increase in structure and/or power consumption of the error correction circuit.SOLUTION: An error correction circuit comprises: input means 153 for inputting an odd number of pieces of redundant binary information in current values; conversion means 151 for converting the sum of the odd number of current values input via the input means into voltage; and first determination means 152 for outputting binary information according to whether the voltage output by the conversion means is equal to or more than a first preset threshold.

30. 发明专利

JP4454890B2 Decoding circuit and a communication device 有权
公开(公告)号：JP4454890B2
公开(公告)日：2010-04-21
申请号：JP2001203652
申请日：2001-07-04
申请人：株式会社東芝
发明人：芳浩丹野 , 浩嗣小倉
IPC分类号： H03M7/38 , H03M13/43 , H03M13/45 , H04B3/06 , H04J13/00 , H04L1/08

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