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21. 发明申请

US20040185665A1 Fabrication method of semiconductor wafer 有权
标题翻译：半导体晶圆的制造方法
公开(公告)号：US20040185665A1
公开(公告)日：2004-09-23
申请号：US10792884
申请日：2004-03-05
申请人： FUJI ELECTRIC HOLDINGS CO., LTD. , SHIN-ETSU HANDOTAI CO., LTD.
发明人： Daisuke Kishimoto , Susumu Iwamoto , Katsunori Ueno , Ryosuke Shimizu , Satoshi Oka
IPC分类号： H01L021/76 , H01L021/20 , C30B001/00 , H01L021/36 , H01L021/302 , H01L021/461
CPC分类号： H01L29/0634 , C30B25/18 , C30B29/06 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/3065 , H01L29/045 , H01L29/0688
摘要： A fabrication method of a semiconductor wafer can fill trenches formed in a semiconductor substrate with an epitaxial film with high crystal quality without leaving cavities in the trenches. The trenches are formed in the first conductivity type semiconductor substrate. Planes exposed inside the trenches are made clean surfaces by placing the substrate in a gas furnace, followed by supplying the furnace with an etching gas and carrier gas, and by performing etching on the exposed planes inside the trenches by a thickness from about a few nanometers to one micrometer. The trenches have a geometry opening upward through the etching. Following the etching, a second conductivity type semiconductor is epitaxially grown in the trenches by supplying the furnace with a growth gas, etching gas, doping gas and carrier gas, thereby filling the trenches. Instead of making the trenches slightly-opened upward, their sidewalls may be made planes enabling facet formation.
摘要翻译：半导体晶片的制造方法可以用具有高晶体质量的外延膜填充在半导体衬底中形成的沟槽，而不会在沟槽中留下空洞。沟槽形成在第一导电型半导体衬底中。通过将衬底放置在气体炉中，然后向炉内供应蚀刻气体和载气，并且通过在沟槽内的暴露平面上蚀刻约几纳米的厚度，将暴露在沟槽内的平面制成干净的表面至一微米。沟槽具有通过蚀刻向上的几何形状。在蚀刻之后，通过向炉提供生长气体，蚀刻气体，掺杂气体和载气，从而在沟槽中外延生长第二导电型半导体，由此填充沟槽。不是使沟槽向上略微打开，它们的侧壁可以制成使得能够形成小平面的平面。

22. 发明申请

US20040175933A1 Method of forming wiring structure 审中-公开
标题翻译：形成布线结构的方法
公开(公告)号：US20040175933A1
公开(公告)日：2004-09-09
申请号：US10778111
申请日：2004-02-17
申请人： SANYO ELECTRIC CO., LTD.
发明人： Yoshinori Shishida , Hiroyuki Watanabe
IPC分类号： H01L021/20
CPC分类号： H01L21/76828 , H01L21/76801 , H01L21/76808 , H01L21/76838
摘要： A method of forming a wiring structure capable of inhibiting a photoresist film for forming an opening from a pattern failure resulting from nitrogen compound gas is obtained. This method of forming a wiring structure comprises steps of forming a first insulator film and a gas permeation suppressive film for suppressing permeation of gas containing nitrogen on a first wiring layer, forming a first opening through the first insulator film and the gas permeation suppressive film, performing at least either heat treatment or retention under a vacuum after forming the first opening, and thereafter forming a second opening through at least the first insulator film.
摘要翻译：获得了能够抑制由氮化合物气体导致的图案破坏而形成开口的光致抗蚀剂膜的布线结构的方法。这种形成布线结构的方法包括以下步骤：形成第一绝缘膜和用于抑制含氮气体在第一布线层上的渗透的气体渗透抑制膜，通过第一绝缘膜和气体渗透抑制膜形成第一开口，在形成第一开口之后，在真空下进行至少热处理或保持，然后通过至少第一绝缘膜形成第二开口。

23. 发明申请

US20040175905A1 Method of forming thin film using atomic layer deposition 审中-公开
标题翻译：使用原子层沉积法形成薄膜的方法
公开(公告)号：US20040175905A1
公开(公告)日：2004-09-09
申请号：US10793715
申请日：2004-03-03
发明人： Seok-Jun Won , Yong-Kuk Jeong , Dae-Jin Kwon
IPC分类号： C23C016/00 , H01L021/20
CPC分类号： C23C16/515 , C23C16/40 , C23C16/45542
摘要： Provided is an atomic layer deposition (ALD) method for forming a thin film using two types of reactants that are different in surface adsorptivity for a source material. According to the ALD method, first, a source material is fed into a reaction chamber and then undergoes first purging. Next, a first reactant with good surface adsorptivity for the source material and a second reactant with poor surface adsorptivity for the source material are fed into the reaction chamber. The second reactant may be fed simultaneously with the first reactant or after the purging of the first reactant. Next, a radio frequency is applied to the reaction chamber to thereby transform the second reactant into a plasma state. Next, the reaction chamber is subjected to a second purging. If the thickness of a deposited film is not sufficient, the above-described processes are repeated.
摘要翻译：提供了使用对源材料的表面吸附性不同的两种类型的反应物形成薄膜的原子层沉积（ALD）方法。根据ALD方法，首先将源材料进料到反应室中，然后进行第一次清洗。接下来，将具有对源材料具有良好的表面吸附性的第一反应物和对源材料具有差的表面吸附性的第二反应物进料到反应室中。第二反应物可以与第一反应物同时进料或在第一反应物的清洗之后进料。接下来，将射频施加到反应室，从而将第二反应物转变成等离子体状态。接下来，对反应室进行第二次净化。如果沉积膜的厚度不足，则重复上述处理。

24. 发明申请

US20040173876A1 Micro-electro-mechanical system (MEMS) variable capacitor apparatuses, systems and related methods 有权
标题翻译：微机电系统（MEMS）可变电容器装置，系统及相关方法
公开(公告)号：US20040173876A1
公开(公告)日：2004-09-09
申请号：US10736283
申请日：2003-12-15
发明人： Francois-Xavier Musalem , Arthur S. Morris III , John Richard Gilbert , Siebe Bouwstra , Randy J. Richards
IPC分类号： H01L021/20 , H01L029/93
CPC分类号： H01G5/16 , H01G5/04 , H01G5/08 , H01G5/10 , H01G5/18 , H01G5/38 , H01P1/127
摘要： Micro-electro-mechanical system (MEMS) variable capacitor apparatuses, system and related methods are provided.
摘要翻译：提供微机电系统（MEMS）可变电容器装置，系统及相关方法。

25. 发明申请

US20040161888A1 MULTI-RESISTIVE STATE MATERIAL THAT USES DOPANTS 失效
标题翻译：使用DOPANTS的多电阻状态材料
公开(公告)号：US20040161888A1
公开(公告)日：2004-08-19
申请号：US10604606
申请日：2003-08-04
申请人： UNITY SEMICONDUCTOR CORPORATION
发明人： Darrell Rinerson , Wayne Kinney , Christophe J. Chevallier , Steven W. Longcor , Edmond R. Ward , Steve Kuo-Ren Hsia
IPC分类号： H01L021/00 , H01L021/8238 , H01L021/20
CPC分类号： G11C13/003 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/2418 , H01L27/2436 , H01L45/10 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/165
摘要： A multi-resistive state material that uses dopants is provided. A multi-resistive state material can be used in a memory cell to store information. However, a multi-resistive state material may not have electrical properties that are appropriate for a memory device. Intentionally doping a multi-resistive state material to modify the electrical properties can, therefore, be desirable.
摘要翻译：提供了使用掺杂剂的多阻态材料。可以在存储器单元中使用多电阻状态材料来存储信息。然而，多阻态材料可能不具有适合于存储器件的电气特性。因此，有意地掺杂多电阻状态材料以改变电性能是可取的。

26. 发明申请

US20040157435A1 Methods of forming metal lines in semiconductor devices 失效
标题翻译：在半导体器件中形成金属线的方法
公开(公告)号：US20040157435A1
公开(公告)日：2004-08-12
申请号：US10749650
申请日：2003-12-30
发明人： Tae-Hee Park
IPC分类号： H01L021/20 , H01L021/44
CPC分类号： H01L21/32139 , C23F1/02 , C23F1/12 , H01L21/32136 , H01L21/76838
摘要： Methods for forming metal lines in semiconductor devices are disclosed. One example method may include forming a lower adhesive layer on a semiconductor substrate; forming a metal layer including aluminum on the lower adhesive layer; forming an anti-reflection layer on the metal layer; forming a photomask on the anti-reflection layer; performing an initial etching, a main etching and an over-etching for the anti-reflection layer, the metal layer and the lower adhesive layer, respectively, in a region which is not protected by the photomask, using C3F8 as a main etching gas; and removing the photomask residual on the anti-reflection layer.
摘要翻译：公开了在半导体器件中形成金属线的方法。一个示例性方法可以包括在半导体衬底上形成下部粘合剂层; 在下粘合剂层上形成包括铝的金属层; 在金属层上形成防反射层; 在防反射层上形成光掩模; 在C3F8作为主要蚀刻气体的情况下，在未被光掩模保护的区域内分别进行防反射层，金属层和下部粘合剂层的初始蚀刻，主蚀刻和过蚀刻; 并去除防反射层上的光掩模残留物。

27. 发明申请

US20040157392A1 CAPACITOR IN AN INTERCONNECT SYSTEM AND METHOD OF MANUFACTURING THEREOF 有权
标题翻译：互连系统中的电容器及其制造方法
公开(公告)号：US20040157392A1
公开(公告)日：2004-08-12
申请号：US10248833
申请日：2003-02-24
发明人： MING-YIN HAO , TRI-RUNG YEW , COMING CHEN , TSONG-MINN HSIEH , NAI-CHEN PENG , JIH-CHENG YEH
IPC分类号： H01L021/20 , H01L021/4763 , H01L021/8242
CPC分类号： H01L28/60 , H01L21/76807 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.
摘要翻译：描述了在互连系统中具有电容器的集成器件的制造方法。至少第一露出金属线和第二金属线设置在绝缘层中。堆叠层并图案化以在第二金属线上形成膜堆叠结构。在膜堆叠结构，第一金属线和绝缘层之上形成金属间介电层。至少第一双镶嵌互连和第二双镶嵌互连分别形成在第一金属线和薄膜堆叠结构的上方并与之接触。

28. 发明申请

US20040157388A1 Semiconductor memory device and method for fabricating the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20040157388A1
公开(公告)日：2004-08-12
申请号：US10749750
申请日：2003-12-30
发明人： Seo-Min Kim , Cheol-Kyu Bok
IPC分类号： H01L021/8242 , H01L021/20 , H01L029/00 , H01L021/4763 , H01L023/48 , H01L029/40
CPC分类号： H01L27/10855 , H01L21/768 , H01L27/101 , H01L27/10808 , H01L27/10852 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device and a method for fabricating the same. Particularly, the semiconductor memory device includes at least two capacitors to decrease the thickness of an insulation layer and increase the size of each capacitor, wherein the thickness of the insulation layer and the size of the capacitor are factors for increasing parasitic capacitance and leakage currents. Also, the two capacitors are arranged diagonally, thereby widening the width of each capacitor formed. Furthermore, in forming double capacitors according to the preferred embodiment of the present invention, an additional reticle is not required to form the contact holes for each capacitor due to their inverted disposition relationship.
摘要翻译：一种半导体存储器件及其制造方法。特别地，半导体存储器件包括至少两个电容器以减小绝缘层的厚度并增加每个电容器的尺寸，其中绝缘层的厚度和电容器的尺寸是增加寄生电容和漏电流的因素。此外，两个电容器对角布置，从而加宽形成的每个电容器的宽度。此外，在根据本发明的优选实施例的形成双电容器中，由于它们的倒置配置关系，不需要额外的掩模版来形成每个电容器的接触孔。

29. 发明申请

US20040147099A1 Method of producing semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20040147099A1
公开(公告)日：2004-07-29
申请号：US10756403
申请日：2004-01-14
申请人： FUJITSU LIMITED
发明人： Hiroshi Hashimoto , Kazuhiko Takada
IPC分类号： H01L021/20
CPC分类号： H01L27/11526 , H01L21/76229 , H01L21/823462 , H01L27/105 , H01L27/11546
摘要： A method for producing a semiconductor device is disclosed that is capable of improving device isolation capability of a device isolation film, and enables effective formation of gate insulating films having different film thicknesses. This method can be used in fabricating a semiconductor device having non-volatile memories with logic elements embedded. As one embodiment, a substrate protection film is formed on a silicon substrate, then an oxide film is formed in a flash cell region with a logic region being covered by the substrate protection film. Next, in the logic region, an intermediate oxide film is formed in a thick film region of the logic region with a thin film region of the logic region being covered by the substrate protection film. Then, the substrate protection film in the thin film region of the logic region is removed, and an oxide film is formed therein. At the same time, the oxide film already in the thick film region is oxidized again, and this results in a thicker oxide film in the thick film region.
摘要翻译：公开了一种能够提高器件隔离膜的器件隔离能力的半导体器件的制造方法，能够有效地形成膜厚不同的栅极绝缘膜。该方法可用于制造具有嵌入逻辑元件的非易失性存储器的半导体器件。作为一个实施例，在硅衬底上形成衬底保护膜，然后在闪存单元区域中形成氧化物膜，其中逻辑区域被衬底保护膜覆盖。接下来，在逻辑区域中，在逻辑区域的厚膜区域中形成中间氧化膜，其中逻辑区域的薄膜区域被衬底保护膜覆盖。然后，除去逻辑区域的薄膜区域中的衬底保护膜，并在其中形成氧化物膜。同时，已经在厚膜区域中的氧化膜再次氧化，这导致厚膜区域中的氧化膜厚度较厚。

30. 发明申请

US20040147086A1 Methods and apparatus for forming rhodium-containing layers 有权
标题翻译：形成含铑层的方法和装置
公开(公告)号：US20040147086A1
公开(公告)日：2004-07-29
申请号：US10755097
申请日：2004-01-09
申请人： MICRON TECHNOLOGY, INC.
发明人： Stefan Uhlenbrock , Eugene P. Marsh
IPC分类号： H01L021/20
CPC分类号： H01L21/76843 , C23C16/16 , C23C16/18 , H01L21/28556 , H01L21/28568 , H01L21/32051 , H01L21/7687 , H01L27/10811 , H01L27/10855 , H01L28/55 , H01L28/65 , H01L28/75
摘要： A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect surrounding materials from oxidation during oxidative recrystallization steps and protect cell dielectrics from loss of oxygen during high temperature processing steps. Also provided are methods for CVD co-deposition of platinum-rhodium alloy diffusion barriers.
摘要翻译：提供了使用式LyRhYz的配合物在诸如半导体晶片的基板上形成含铑层的方法。还提供了化学气相共沉积的铂 - 铑合金屏障和用于集成电路的电池电介质的电极，特别是用于DRAM电池电容器。在氧化再结晶步骤期间，合金屏障保护周围材料不被氧化，并在高温处理步骤中保护电池电介质免受氧气损失。还提供了用于铂 - 铑合金扩散阻挡层的CVD共沉积的方法。

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