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21. 发明专利

GB1413739A ADDRESS CONVERSION UNITS AND DATA PROCESSING SYSTEMS EMBODYING THE SAME 未知
公开(公告)号：GB1413739A
公开(公告)日：1975-11-12
申请号：GB4734773
申请日：1973-10-10
申请人： DIGITAL EQUIPMENT CORP
IPC分类号： G06F12/10 , G06F12/02 , G06F13/08
摘要： 1413739 Virtual addressing systems DIGITAL EQUIPMENT CORP 10 Oct 1973 [10 Oct 1972] 47347/73 Heading G4A Apparatus for converting a virtual address to a physical address of a page in a random access memory comprises means for using a first part of the virtual address to read from a store a base page address which is then added to a second part of the address. The resulting sum is concatenated with a third part of the address to provide the physical address. A data processing system employing the apparatus may operate in any of a number of modes, and the related programs are stored in corresponding sections of a random access core memory. The page length is alterable. A set of page address registers is allotted to each mode. When a virtual address is received its first few high order bits e.g. 13-15, Fig. 4, are used to access the corresponding register in the set of registers pertinent to the present mode. The base page address is read from the register to a binary full adder where it is added to the second part, e.g. bits 6-12 of the virtual address. The second part has fewer bits than does the base page address. The resulting sum is concatenated with the third part, e.g. bits 0-5 of the virtual address, so providing a physical address of greater bit length than the virtual address. When a base page address is read from a register a page descriptor is also provided. The descriptor disclosed includes a 3-bit indication of the manner in which the page may be accessed, a page length indicator defining the number of blocks of 32 words comprising the page, and a 1-bit indicating whether the words in the page progress from the top or bottom of the page. By reference to the word direction bit and the page length indicator it is determined whether the block number indicated by bits 6-12 of the virtual address lies within the present page length. If it does not, a new page address replaces that in the selected page address register. This address is that of an unused area in the random access memory sufficiently large to accommodate the required number of blocks of words. The page length word in the descriptor is correspondingly updated.

22. 发明专利

DE2259994A1 未知
公开(公告)号：DE2259994A1
公开(公告)日：1973-07-19
申请号：DE2259994
申请日：1972-12-07
申请人： INT STANDARD ELECTRIC CORP
发明人： KOBUS STANISLAS , JANSSENS JULIAEN LEO GERARD , ZVILE WILLY CHARLES JACQUES
IPC分类号： G06F7/74 , G06F9/308 , G06F9/355 , H04Q3/545 , G06F13/08

23. 发明专利

DE1549463B1 未知
公开(公告)号：DE1549463B1
公开(公告)日：1970-10-08
申请号：DE1549463
申请日：1967-03-25
申请人： IBM
发明人： CRAFT JOHN LEWIS
IPC分类号： G06F13/12 , G06F13/08
摘要： 1,144,407. Computer input channel. INTERNATIONAL BUSINESS MACHINES CORP. 22 Feb., 1967 [28 March, 1966], No. 8578/67. Headings G4A and G4C. In a data processing system, a part of an input data word is selectively routed by switching means to an address register to address a storage location for the word, the switching means being capable of connecting any one of a set of lines on which the word appears to any one of the storage positions of the address register. A 51-line real-time input channel to a computer leads to a matrix switch which can permute the connections between these 51 input lines and 51 output lines, 36 of which lead to a data register and 15 to a channel address counter. The contents of the data register can be stored in a core store at an address specified by the channel address counter. The matrix switch contains 51 six-bit control registers, one for each input line, to gate the input line to any one of the output lines. The control registers can be set by programmed control words via the data register. Each 36-bit control word has three 12-bit portions, each portion relating to a respective 17 of the 51 control registers. Six of the 12 bits are placed in a control register selected by 5 of the other bits. The remaining bit is set to 1 unless none of the 17 registers is to respond to the 12 - bit portion. If this remaining bit is 1 and the register-selection bits are all 0, all 17 registers are zeroized (so that they will not gate their respective bits from the input channel to any of the output lines). Experimental values on the input channel can thus be used to address the core store, the contents of the addressed locations being incremented, to keep counts of the various possible experimental values. A high-order carry enables action to be taken after a particular member of particular values have been received by prestoring the complement of the particular number in the appropriate location. Similarly, sums of experimental values can be accumulated. The experimental values may be analogue values digitized and may come from a matrix of photoconductors or &c.

24. 发明专利

NL6901996A 未知
公开(公告)号：NL6901996A
公开(公告)日：1969-08-12
申请号：NL6901996
申请日：1969-02-07
IPC分类号： B07C3/00 , G06F17/30 , H03M7/00 , G06F13/00 , B07C3/18 , G06F7/30 , G06F13/08

25. 发明授权

US4698749A RAM memory overlay gate array circuit 失效
标题翻译： RAM存储器覆盖门阵列电路
公开(公告)号：US4698749A
公开(公告)日：1987-10-06
申请号：US789213
申请日：1985-10-18
申请人： Nataraj Bhadriraju
发明人： Nataraj Bhadriraju
IPC分类号： G06F12/06 , G06F13/08
CPC分类号： G06F12/0623
摘要： This circuitry expands the memory addressing arrange of a microprocessor beyond its directly addressable memory capacity. This circuit uses the status outputs of the microprocessor to segregate memory accesses for program code instructions from accesses for other data. This segregation scheme assigns different memory banks to program code instructions and to data. Memory reads and writes for scratch pad data are performed from one bank of memory. Memory reads for program code instructions are performed from a separate memory bank. This memory bank technique can double the size of a microprocessor's directly addressable memory without changing the microprocessor's architecture. This circuitry is suitable for implementation with CMOS gate array technology.
摘要翻译：该电路将微处理器的存储器寻址布置扩展到超出其直接寻址的存储器容量。该电路使用微处理器的状态输出将程序代码指令的存储器访问隔离到其他数据的访问中。该分离方案分配不同的存储体来编程代码指令和数据。从一组存储器执行用于暂存数据的存储器读取和写入。程序代码指令的存储器读取是从单独的存储体执行的。这种存储器技术可以使微处理器的直接寻址存储器的尺寸翻倍，而不改变微处理器的架构。该电路适用于CMOS门阵列技术的实现。

26. 发明授权

US4509118A Method and apparatus for defining magnetic disk track field lengths using a programmable counter 失效
标题翻译：使用可编程计数器定义磁盘轨迹场长度的方法和装置
公开(公告)号：US4509118A
公开(公告)日：1985-04-02
申请号：US382000
申请日：1982-05-25
申请人： William H. Shenk
发明人： William H. Shenk
IPC分类号： G06F3/06 , G06F13/08
CPC分类号： G06F3/0607 , G06F3/064 , G06F3/0676
摘要： A method and apparatus for defining magnetic disk track field lengths using a programmable counter. Use of a programmable counter in a disk controller permits a reduction in the amount of combinational logic that would otherwise be required to be able to perform the various formatting, reading and writing operations involved in use of just one type of disk and makes it possible to perform these operations on a wide variety of disks having different track and sector formats.
摘要翻译：一种使用可编程计数器定义磁盘轨道场长度的方法和装置。在磁盘控制器中使用可编程计数器允许减少组合逻辑的量，否则这些组合逻辑将能够执行仅使用一种类型的磁盘所涉及的各种格式化，读取和写入操作，并且可以在具有不同轨道和扇区格式的各种磁盘上执行这些操作。

27. 发明授权

US4126894A Memory overlay linking system 失效
标题翻译：内存覆盖链接系统
公开(公告)号：US4126894A
公开(公告)日：1978-11-21
申请号：US769612
申请日：1977-02-17
申请人： David Cronshaw , James R. Keddy , Jack E. Shemer , William D. Turner
发明人： David Cronshaw , James R. Keddy , Jack E. Shemer , William D. Turner
IPC分类号： G06F12/08 , G06F12/12 , G06F13/08 , G06F9/10
CPC分类号： G06F12/0862 , G06F12/123 , G06F2212/6024
摘要： A mapping arrangement for memory overlay wherein the address coordinates are referenced to a main serial memory. This main memory is partitioned into pages of equal size. An accelerator memory is concurrently loaded with a few pages representing a small portion of the main memory contents and is periodically overlayed with new memory contents on a page-at-a-time basis as the using system demands. During this overlay the fields of the accelerator memory are inscribed at corresponding main memory address coordinates together with code bits indicating whether certain memory fields go together and are therefore promoted as a single unit. The resulting effect is to cause an apparent increase in page size since more than one page is promoted as a consequence of a reference to a page not contained in the accelerator memory.
摘要翻译：用于存储器覆盖的映射布置，其中地址坐标被引用到主串行存储器。该主存储器被分成相同大小的页面。加速器存储器被同时加载几页，表示主存储器内容的一小部分，并且随着使用系统的需要，在一个页面上周期性地重叠新的存储器内容。在该覆盖期间，加速器存储器的各个字段与相应的主存储器地址坐标一起被记录在一起，其中代码位指示某些存储器区域是否一起存在，因此被提升为单个单元。由于引用了不包含在加速器存储器中的页面的结果，由于多个页面被提升，所以产生的效果是导致页面大小明显增加。

28. 发明授权

US3958227A Control store system with flexible control word selection 失效
标题翻译：具有灵活控制字选择的控制存储系统
公开(公告)号：US3958227A
公开(公告)日：1976-05-18
申请号：US508797
申请日：1974-09-24
申请人： Charles W. Evans
发明人： Charles W. Evans
IPC分类号： G06F9/28 , G06F9/22 , G06F9/26 , G05B19/24 , G06F13/08
CPC分类号： G06F9/267
摘要： A branch-address translation register (BAXR) is loaded by a current or a prior control word field. A word selection decoder circuit receives the BAXR outputs and combines them with machine-status signals to generate a word selection signal for selecting a control word from a currently accessed branch group in the control store. A BAXR switching circuit is also provided so that any control word can switch off the BAXR output and cause a control word selection without translation. The invention can obtain any required degree of addressing flexibility in microcode branch selection, i.e. from partial to total flexibility.

29. 发明授权

US3833930A Input/output system for a microprogram digital computer 失效
标题翻译： MICROPROGRAM数字计算机的输入/输出系统
公开(公告)号：US3833930A
公开(公告)日：1974-09-03
申请号：US32310773
申请日：1973-01-12
申请人： BURROUGHS CORP
发明人： MACKER J
IPC分类号： G06F13/12 , G06F15/78 , G06K17/00 , G06F13/08
CPC分类号： G06F13/122
摘要： An input/output sub-system for a digital data processing system having a microprogrammed processor and main memory in which the processor functions as a multiplexor for transferring data between a plurality of peripheral devices and the memory. The I/O controls for the peripheral devices share a common bus to the processor. The controls are slaved to the processor and operate to send or receive information over the common bus only in response to commands from the processor. However, any I/O control unit can signal the processor that it needs service. Each command addressed to one of the I/O control units is followed by status information returned on the bus to the processor by the I/O control. In addition, the status of an I/O control can be tested on special command from the processor. Each I/O control is buffered for storage of a block of data. A reference address pointing to the location of the Input/Output Descriptor in memory being executed by the processor is transferred to the control and stored in the buffer. It is returned to the processor after a Service Request by the control is acknowledged by the processor.
摘要翻译：一种用于具有微程序处理器和主存储器的数字数据处理系统的输入/输出子系统，其中处理器用作用于在多个外围设备和存储器之间传送数据的多路复用器。外围设备的I / O控制器共享一个公共总线到处理器。控制器从属于处理器，并且仅在响应来自处理器的命令时，通过公共总线进行信号发送或接收信息。但是，任何I / O控制单元都可以向处理器通知需要的服务。寻址到其中一个I / O控制单元的每个命令之后是通过I / O控制在总线上返回到处理器的状态信息。此外，I / O控制的状态可以通过处理器的特殊命令进行测试。缓冲每个I / O控制以存储数据块。指向由处理器执行的存储器中的输入/输出描述符的位置的参考地址被传送到控制并存储在缓冲器中。在控制器通过处理器确认服务请求后，它返回到处理器。

30. 发明授权

US4747044A Direct execution of software on microprogrammable hardware 失效
标题翻译：在可编程硬件上直接执行软件
公开(公告)号：US4747044A
公开(公告)日：1988-05-24
申请号：US643512
申请日：1984-08-23
申请人： Carson T. Schmidt , Chenyu Chao , Gregory D. Brinson , Jerrold L. Allen , Barry L. Loges , Timothy G. Goldsbury , Robert O. Gunderson , Jerry K. Herreweyers
发明人： Carson T. Schmidt , Chenyu Chao , Gregory D. Brinson , Jerrold L. Allen , Barry L. Loges , Timothy G. Goldsbury , Robert O. Gunderson , Jerry K. Herreweyers
IPC分类号： G06F9/22 , G06F12/10 , G06F13/08
CPC分类号： G06F9/22 , G06F12/1063
摘要： A data processing system including an addressable main memory for storing data and directly executable microinstructions, and a central processing chip having a data interface terminal and an instruction terminal. A processor memory bus is connected between the main addressable memory and the central processing chip data interface terminal. An instruction bus is connected between the central processing chip instruction terminal and the addressable memory.The directly executable microinstructions in the addressable main memory are fetched from the main memory by an apparatus which includes an instruction address circuit connected to the processor memory bus and the instruction bus. The instruction address circuit includes a virtual address register circuit for receiving a portion of a virtual address from the instruction bus, and a portion of the mentioned virtual address from the processor memory bus. A virtual-to-real translation circuit in the instruction address circuit translates the virtual address in the virtual address register to a real address in the addressable memory from which an executable microinstruction may be fetched.
摘要翻译：一种数据处理系统，包括用于存储数据和可直接执行的微指令的可寻址主存储器，以及具有数据接口终端和指令终端的中央处理芯片。处理器存储器总线连接在主可寻址存储器和中央处理芯片数据接口终端之间。指令总线连接在中央处理芯片指令终端和可寻址存储器之间。可寻址主存储器中的可直接执行的微指令通过包括连接到处理器存储器总线和指令总线的指令地址电路的装置从主存储器中取出。指令地址电路包括用于从指令总线接收虚拟地址的一部分的虚拟地址寄存器电路和来自处理器存储器总线的所述虚拟地址的一部分。指令地址电路中的虚拟到实际的转换电路将虚拟地址寄存器中的虚拟地址转换为可寻址存储器中的可实际地址，可从中获取可执行的微指令。

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