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21. 发明申请

WO99050963A2 TURBO ENCODING/DECODING DEVICE AND METHOD FOR PROCESSING FRAME DATA ACCORDING TO QoS 审中-公开
标题翻译： TURBO编码/解码装置和根据QoS处理帧数据的方法
公开(公告)号：WO99050963A2
公开(公告)日：1999-10-07
申请号：PCT/KR1999/000154
申请日：1999-03-31
IPC分类号： H03M13/13 , H03M13/00 , H03M13/27 , H03M13/29 , H03M13/43 , H03M13/49 , H04B7/24 , H04J3/00 , H04J13/00 , H04L1/00 , H04W28/06 , H04B
CPC分类号： H04L1/005 , H03M13/27 , H03M13/2789 , H03M13/2903 , H03M13/2957 , H03M13/35 , H03M13/43 , H03M13/49 , H04L1/0007 , H04L1/0047 , H04L1/0055 , H04L1/0059 , H04L1/0066 , H04L1/0071
摘要： A turbo channel encoding/decoding device for a CDMA communication system. The device segments an input frame into multiple sub frames of an appropriate length when the input data frame is very long, and then encodes and decodes the sub frames. Otherwise, when the input data frames are very short, the device combines input frames into one super frame of an appropriate length and then encodes and decodes the super frame. After frame encoding/decoding, the frames are recombined into the original input frames.
摘要翻译：一种用于CDMA通信系统的turbo信道编码/解码装置。当输入数据帧非常长时，该设备将输入帧划分成适当长度的多个子帧，然后对子帧进行编码和解码。否则，当输入数据帧非常短时，设备将输入帧组合成一个适当长度的超帧，然后对超帧进行编码和解码。在帧编码/解码之后，帧被重新组合成原始输入帧。

22. 发明公开

KR1020080003631A 데이터 오류 정정 회로 및 방법, 이를 포함하는 집적 회로 有权
标题翻译：数据错误校正电路及其方法及其集成电路
公开(公告)号：KR1020080003631A
公开(公告)日：2008-01-08
申请号：KR1020060062100
申请日：2006-07-03
申请人： 삼성전자주식회사
发明人： 강원식 , 김성철
IPC分类号： G06F11/22
CPC分类号： H03M13/43
摘要： A data error correction circuit and a method thereof and an integrated circuit having the same are provided to correct data errors by ESD(Electrostatic Discharge) and EMI(Electromagnetic Interference) through a plurality of registers. A data error correction circuit(700) comprises a data detecting unit and a data correction unit. The data detecting unit(400) determines whether all data values stored in a plurality of registers are same. If all the data values are not same, the data correcting unit(710) calculates a correction value to correct the data value of the registers based on the data value stored respectively in the registers.
摘要翻译：提供数据纠错电路及其方法和具有该数据纠错电路的集成电路，以通过多个寄存器通过ESD（静电放电）和EMI（电磁干扰）来校正数据错误。数据纠错电路（700）包括数据检测单元和数据校正单元。数据检测单元（400）确定存储在多个寄存器中的所有数据值是否相同。如果所有数据值不相同，则数据校正单元（710）根据分别存储在寄存器中的数据值，计算校正值以校正寄存器的数据值。

23. 发明专利

JP5324470B2 Decoding device and method of the complete difference set cyclic code and difference set cyclic code 有权
公开(公告)号：JP5324470B2
公开(公告)日：2013-10-23
申请号：JP2009544813
申请日：2008-03-31
申请人：サムスンエレクトロニクスカンパニーリミテッド
发明人：ヴァシリー・プリビロヴ
IPC分类号： H03M13/15
CPC分类号： H04L1/0045 , H03M13/15 , H03M13/3746 , H03M13/43 , H03M13/618
摘要： A decoding apparatus includes a decoder register for receiving data having a codeword including null data bits, and decoding the received data while shifting Bit Under Decoding (BUD) by one bit. A connection unit outputs a check result by applying a predetermined check equation to the data output from the decoder register. A majority logic unit for determines if an error is detected according to the check result output from the connection unit, and outputs the determination result. An error information unit determines if there is an error in the received data and if there is an uncorrectable error in the decoded data.

24. 发明专利

JPS59181841A Error correcting and decoding system 失效
标题翻译：错误修正和解码系统
公开(公告)号：JPS59181841A
公开(公告)日：1984-10-16
申请号：JP5400283
申请日：1983-03-31
申请人： Nippon Hoso Kyokai
发明人： YAMADA TSUKASA
IPC分类号： H03M13/00 , H03M13/43
CPC分类号： H03M13/43
摘要： PURPOSE:To perform correction and decoding until a prescribed threshold value is obtained by adding a subtraction circuit to a majority decision circuit so as to set a threshold value to be decided of the majority decision circuit to a specific value within the number of the input devices of the majority decision circuit and subtracting this threshold value to be decided via the subtraction circuit after cyclic correction. CONSTITUTION:A CPU sets a threshold value designating signal 129 to ''17''. Then, the CPU generates a start signal 110 to reset 124 a syndrome register 106. Further, the CPU loads sequentially 1-packet 272-bit information by 16-bit each in 17 divisions. the loaded data is superimposed on a data 114 before error correction to generate a load instruction 111. A load gate signal 120 is generated based on this signal 111 to attain data loading before error correction and 16-bit shift to registers 103 and 106. When this procedure is repeated 17 times, the generated syndrome is stored in the register 106. Then, the correcting operation is commanded by the CPU. After the error correction of 16-bit is performed by a correcting signal 113, the CPU reads a data 115.
摘要翻译：目的：执行校正和解码，直到通过将减法电路加到多数决定电路而获得规定的阈值，以便将多数判定电路的判定阈值设定为输入装置的数量内的特定值并减去该循环校正后通过减法电路决定的阈值。构成：CPU将阈值指定信号129设定为“17”。然后，CPU产生启动信号110以复位124个校正子寄存器106.此外，CPU以17个分区顺序加载1分组272位信息16位。加载的数据被叠加在错误校正之前的数据114上以产生加载指令111.基于该信号111产生加载门信号120，以在纠错之前获得数据加载，并且向寄存器103和106进行16位移位。当该过程重复17次，将生成的校正子存储在寄存器106中。然后，由CPU命令校正操作。在通过校正信号113执行16位的纠错之后，CPU读取数据115。

25. 发明专利

JP5543170B2 Method of error correction and error detection of binary data 有权
公开(公告)号：JP5543170B2
公开(公告)日：2014-07-09
申请号：JP2009237428
申请日：2009-10-14
申请人：トムソンライセンシングThomson Licensing
发明人：タイスオリバー , シャオ−ミンチェン , ゲオルギマルコ
IPC分类号： H03M13/19 , G11B20/18
CPC分类号： H03M13/1162 , H03M13/1105 , H03M13/17 , H03M13/2906 , H03M13/43

26. 发明专利

JPS61131270A Block address correcting circuit 失效
标题翻译：块地址纠正电路
公开(公告)号：JPS61131270A
公开(公告)日：1986-06-18
申请号：JP25346384
申请日：1984-11-30
申请人： Sony Corp
发明人： YAMAMOTO YOSHIKAZU
IPC分类号： G11B20/12 , H03M13/27 , H03M13/43
CPC分类号： H03M13/43
摘要： PURPOSE:To make a block address correction stronger by obtaining a majority of a difference signal between an output of a counter and a block address in the input data by a reference block signal and calculating a block address from the decision output. CONSTITUTION:Since a block address code added to a block each has a continuity, the difference between an output of a counter 13 counted up by a reference block signal and a block address in input data DIN is to be a constant value. The difference is obtained by a subtracter circuit 12 and the difference of a block address, to which influences of transmission errors are given, will not be able to go to a prescribed value. Then, by a majority logic circuit 16, the majority of a difference signal which is continuous, for example, concerning five blocks, is obtained, a correct difference is determined. The output of a counter 20 counted up by a block signal to the determining difference is added by an adder circuit 19 and the value of a block address is calculated. Consequently, even when error correcting code processing is not executed to a block address code, the block address can be sufficiently corrected.
摘要翻译：目的：通过参考块信号获得计数器的输出和输入数据中的块地址之间的大部分差分信号，并从判定输出计算块地址，使块地址校正更强。构成：由于添加到块的块地址码各自具有连续性，所以通过参考块信号计数的计数器13的输出与输入数据DIN中的块地址之间的差异是恒定值。该差异由减法电路12获得，并且给出了传输误差影响的块地址的差异将不能达到规定值。然后，通过多数逻辑电路16，获得例如关于五个块的连续的差分信号的大部分，确定正确的差异。计数器20的输出通过块信号计数到确定差值，由加法器电路19相加，并且计算块地址的值。因此，即使不对块地址码执行纠错码处理，也可以充分校正块地址。

27. 发明申请

WO2009137754A2 SNR-BASED VARIABLE-THRESHOLD MAJORITY-LOGIC DECORDER 审中-公开
标题翻译：基于SNR的可变阈值主要逻辑判定器
公开(公告)号：WO2009137754A2
公开(公告)日：2009-11-12
申请号：PCT/US2009/043263
申请日：2009-05-08
申请人： AUGUSTA TECHNOLOGY USA, INC. , QIAN, Jing , ZHIGANG, Cao , YANG, Baoguo
发明人： QIAN, Jing , ZHIGANG, Cao , YANG, Baoguo
IPC分类号： H04W28/04
CPC分类号： H03M13/35 , H03M13/3707 , H03M13/43 , H03M13/612
摘要： Apparatus having corresponding methods and tangible computer-readable medium embodying instructions executable by a computer to perform the methods comprise: a receiver adapted to receive a signal representing an input code block, wherein the input code block represents information encoded with a (N, K) difference-set cyclic code, wherein the input code block includes N symbols, and wherein the N symbols represent K bits of the information; an estimator adapted to estimate a signal-to-noise ratio of the signal; a raised- threshold majority-logic decoder adapted to decode the input code block according to a raised-threshold majority-logic decoding algorithm when the signal-to-noise ratio does not exceed a first predetermined threshold; and a variable-threshold majority-logic decoder adapted to decode the input code block according to a variable-threshold majority-logic decoding algorithm when the signal-to-noise ratio exceeds the first predetermined threshold.
摘要翻译：具有相应方法的装置和体现由计算机执行以执行所述方法的指令的有形计算机可读介质包括：接收器，适于接收表示输入码块的信号，其中所述输入码块表示用（N，K）差分集循环码，其中所述输入码块包括N个符号，并且其中所述N个符号表示所述信息的K个比特; 估计器，适于估计所述信号的信噪比; 当信噪比不超过第一预定阈值时，上升阈值多数逻辑解码器适于根据提升阈值多数逻辑解码算法对输入代码块进行解码; 以及可变阈值多数逻辑解码器，其适于在信噪比超过第一预定阈值时根据可变阈值多数逻辑解码算法对输入代码块进行解码。

28. 发明申请

WO2004019579A1 NOISE-ADAPTIVE DECODING 审中-公开
标题翻译：噪声自适应解码
公开(公告)号：WO2004019579A1
公开(公告)日：2004-03-04
申请号：PCT/US2003/025219
申请日：2003-08-13
申请人： VANU, INC. , FELDMAN, Jon , FRIGO, Matteo , ABOU-FAYCAL, Ibrahim
发明人： FELDMAN, Jon , FRIGO, Matteo , ABOU-FAYCAL, Ibrahim
IPC分类号： H04L27/06
CPC分类号： H04L1/0045 , H03M13/00 , H03M13/37 , H03M13/43 , H04L1/0057
摘要： In one aspect the invention is a method for decoding. The method includes receiving encoded data and decoding the encoded data using a noise-adaptive decoder. The data may include first-order Reed Mueller (FORM) based codes. The data may be based on Complementary Code Keying- Using a noise-adaptive decoder may include determining values of a hard decision based on a first decoding process and discarding the values of the hard decision if a noise sensitivity parameter is above a threshold value. The method may further include using a second decoder process if the noise sensitivity parameter is above the threshold value.
摘要翻译：在一个方面中，本发明是用于解码的方法。该方法包括接收编码数据并使用噪声自适应解码器对编码数据进行解码。数据可能包括基于一阶芦苇（米尔）（FORM）的代码。数据可以基于补码键控。使用噪声自适应解码器可以包括基于第一解码过程确定硬判决的值，并且如果噪声灵敏度参数高于阈值则丢弃硬判决的值。如果噪声灵敏度参数高于阈值，则该方法还可以包括使用第二解码器处理。

29. 发明申请

WO9950963A3 TURBO ENCODING/DECODING DEVICE AND METHOD FOR PROCESSING FRAME DATA ACCORDING TO QoS 审中-公开
标题翻译： TURBO编码/解码装置和根据QoS处理帧数据的方法
公开(公告)号：WO9950963A3
公开(公告)日：2000-04-06
申请号：PCT/KR9900154
申请日：1999-03-31
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK CHANG SOO , JEONG JOONG HO , LEE HYEON WOO
IPC分类号： H03M13/13 , H03M13/00 , H03M13/27 , H03M13/29 , H03M13/43 , H03M13/49 , H04B7/24 , H04J3/00 , H04J13/00 , H04L1/00 , H04W28/06 , H04B7/26 , H04L1/18 , H04Q7/32
CPC分类号： H04L1/005 , H03M13/27 , H03M13/2789 , H03M13/2903 , H03M13/2957 , H03M13/35 , H03M13/43 , H03M13/49 , H04L1/0007 , H04L1/0047 , H04L1/0055 , H04L1/0059 , H04L1/0066 , H04L1/0071
摘要： A turbo channel encoding/decoding device for a CDMA communication system. The device segments an input frame into multiple sub frames of an appropriate length when the input data frame is very long, and then encodes and decodes the sub frames. Otherwise, when the input data frames are very short, the device combines input frames into one super frame of an appropriate length and then encodes and decodes the super frame. After frame encoding/decoding, the frames are recombined into the original input frames.
摘要翻译：一种用于CDMA通信系统的turbo信道编码/解码装置。当输入数据帧非常长时，该设备将输入帧划分成适当长度的多个子帧，然后对子帧进行编码和解码。否则，当输入数据帧非常短时，设备将输入帧组合成一个适当长度的超帧，然后对超帧进行编码和解码。在帧编码/解码之后，帧被重新组合成原始输入帧。

30. 发明申请

WO1989009965A1 ERROR DETECTION METHOD FOR SUB-BAND CODING 审中-公开
标题翻译：用于子带编码的错误检测方法
公开(公告)号：WO1989009965A1
公开(公告)日：1989-10-19
申请号：PCT/US1989001142
申请日：1989-03-16
申请人： MOTOROLA, INC.
发明人： MOTOROLA, INC. , MCLAUGHLIN, Michael, Joseph , RASKY, Phillip, David
IPC分类号： G06F11/10
CPC分类号： H04L1/201 , G10L19/005 , G11B20/1833 , H03M13/09 , H03M13/35 , H03M13/43 , H04B1/667 , H04L1/004 , H04L1/0061 , H04L1/0065 , H04L1/007 , H04L1/0071 , H04L1/0072 , H04L2001/0098
摘要： A method and apparatus is disclosed (Fig. 3) for improving the quality of speech samples communicated via sub-band coding utilizing adaptive bit allocation (Fig. 1), by providing error detection only on the adaptive bit allocation information. A first error detection code (340), such as a cyclic redundancy check (CRC), is calculated on the bit allocation parameters (330) in the transmitter (130) and sent to the receiver (180), where a second error detection code (370) is calculated based upon the reconstructed bit allocation parameters (360). The transmitted error detection code is then used to determine (380) if the received bit allocation information is correct, and if not, the frame of speech data is discarded. By protecting only the bit allocation information, additional speech frames may be salvaged from the error-prone channel, thus further increasing speech intelligibility.
摘要翻译：公开了一种用于通过仅利用自适应位分配信息提供错误检测来改善通过使用自适应位分配（图1）的子带编码传送的语音样本的质量的方法和装置（图3）。对发送机（130）中的比特分配参数（330）计算出诸如循环冗余校验（CRC）的第一错误检测码（340），并将其发送到接收机（180），其中第二错误检测码（370）基于重构的比特分配参数（360）来计算。然后，发送的错误检测码用于确定（380）所接收的比特分配信息是否正确，如果不是，则丢弃该语音数据帧。通过仅保护比特分配信息，可以从容易出错的信道中抢救附加语音帧，从而进一步增加语音可懂度。

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