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21. 发明申请

WO2004025695A2 SEMICONDUCTOR DEVICE WITH WIRE BOND INDUCTOR AND METHOD 审中-公开
标题翻译：具有导线键合电感器的半导体装置和方法
公开(公告)号：WO2004025695A2
公开(公告)日：2004-03-25
申请号：PCT/US2002/028883
申请日：2002-09-10
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES L.L.C. , KNAPP, James , CARNEY, Francis , ANDERSON, Harold , WEN, Yenting , NGO, Cang
发明人： KNAPP, James , CARNEY, Francis , ANDERSON, Harold , WEN, Yenting , NGO, Cang
IPC分类号： H01L
CPC分类号： H01L23/645 , H01F17/02 , H01F27/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L27/06 , H01L2223/6611 , H01L2224/05553 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4809 , H01L2224/48091 , H01L2224/48092 , H01L2224/4813 , H01L2224/48247 , H01L2224/484 , H01L2224/48599 , H01L2224/48699 , H01L2224/4903 , H01L2224/49051 , H01L2224/78301 , H01L2224/85047 , H01L2224/8517 , H01L2224/85181 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , H01L2924/19107 , H01L2924/20754 , H01L2924/20755 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device (10) includes a semiconductor die (20) and an inductor (30, 50) formed with a bonding wire (80) attached to a top surface (21) of the semiconductor die. The bonding wire is extended laterally a distance (L30, L50) greater than its height (H30, H50) to define an insulating core (31, 57). In one embodiment, the inductor is extended beyond an edge (35, 39) of the semiconductor die to reduce loading.
摘要翻译：半导体器件（10）包括半导体管芯（20）和电感器（30,50），电感器（30,50）形成有连接到半导体管芯的顶表面（21）的键合引线（80）。键合线横向延伸一个大于其高度（H30，H50）的距离（L30，L50）以限定绝缘芯（31,57）。在一个实施例中，电感器延伸超过半导体管芯的边缘（35,39）以减小负载。

22. 发明申请

WO2004017419A1 VERTICAL GATE SEMICONDUCTOR DEVICE WITH A SELF-ALIGNED STRUCTURE 审中-公开
标题翻译：具有自对准结构的垂直栅极半导体器件
公开(公告)号：WO2004017419A1
公开(公告)日：2004-02-26
申请号：PCT/US2003/023558
申请日：2003-07-28
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES L.L.C.
发明人： GRIVNA, Gordon, M.
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L21/28114 , H01L21/2815 , H01L29/42304 , H01L29/42376 , H01L29/66272 , H01L29/66712 , H01L29/7322 , H01L29/7811
摘要： A transistor (10) is formed in a semiconductor substrate (12) whose top surface (48) is formed with a pedestal structure (24). A conductive material (40) is disposed along a side surface (28) of the pedestal structure to self-align an edge of a source region (45) of the transistor. A dielectric spacer (55) is formed along a side surface (49) of the conductive material to self-align a contact area (56) of the source region. The body region (31) of the transitor is self-aligned to the sidewalls of the pedstal structure. In one embodiment the side surface of the pedestal comprises a recess portion at its base.
摘要翻译：晶体管（10）形成在其顶表面（48）形成有基座结构（24）的半导体衬底（12）中。导电材料（40）沿着基座结构的侧表面（28）设置以自对准晶体管的源极区（45）的边缘。沿着导电材料的侧表面（49）形成电介质间隔物（55），以使源区的接触区域（56）自对准。该过渡体的主体区域（31）与脚蹬结构的侧壁自对准。在一个实施例中，基座的侧表面在其底部包括凹部。

23. 发明申请

WO2003105228A1 SEMICONDUCTOR FILTER CIRCUIT AND METHOD 审中-公开
标题翻译：半导体滤波电路及方法
公开(公告)号：WO2003105228A1
公开(公告)日：2003-12-18
申请号：PCT/US2003/014505
申请日：2003-05-12
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES L.L.C.
发明人： ESCOFFIER, Rene , PEARSE, Jeffrey , ROBB, Francine, Y. , STEFANOV, Evgueniy, Nikolov , ZDEBEL, Peter, J.
IPC分类号： H01L27/02
CPC分类号： H01L27/0251
摘要： A filter circuit (10) is formed on a semiconductor substrate (11) formed with a trench (40) that is lined with a dielectric layer (38). A conductive material (37) is disposed in the trench and coupled to a node (62) to provide a capacitance that modifies a frequency response of an input signal (VIN) to produce a filtered signal (VOUT). An electrostatic discharge device includes an inductor (74) coupled to back to back diodes (17, 18) formed in the substrate to avalanche when a voltage on the node reaches a predetermined magnitude.
摘要翻译：滤波器电路（10）形成在形成有衬有介电层（38）的沟槽（40）的半导体衬底（11）上。导电材料（37）设置在沟槽中并且耦合到节点（62）以提供修改输入信号（VIN）的频率响应以产生滤波信号（VOUT）的电容。静电放电装置包括耦合到形成在基板中的背对背二极管（17,18）的电感器（74），当节点上的电压达到预定的大小时，该电感器雪崩。

24. 发明申请

WO2010011219A2 METHOD OF FORMING A SWITCHING REGULATOR AND STRUCTURE THEREFOR 审中-公开
标题翻译：形成开关稳压器及其结构的方法
公开(公告)号：WO2010011219A2
公开(公告)日：2010-01-28
申请号：PCT/US2008/070874
申请日：2008-07-23
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C. , BASSO, Christophe , CYR, Nicolas
发明人： BASSO, Christophe , CYR, Nicolas
IPC分类号： H02B11/10
CPC分类号： H02M3/33507 , H02M3/33523 , H02M2001/0016 , H02M2001/0025 , Y10T29/49002
摘要： In one embodiment, a power supply controller is configured to receive a sense signal having a negative value that is proportional to the input voltage. The power supply controller uses the sense signal to limit the switch current through the switch responsively to the value of the input voltage.
摘要翻译：在一个实施例中，电源控制器被配置为接收具有与输入电压成比例的负值的感测信号。电源控制器使用感测信号来响应于输入电压的值来限制开关电流通过开关。

25. 发明申请

WO2009070153A1 METHOD AND STRUCTURE OF FORMING A FLUORESCENT LIGHTING SYSTEM 审中-公开
标题翻译：形成荧光灯系统的方法与结构
公开(公告)号：WO2009070153A1
公开(公告)日：2009-06-04
申请号：PCT/US2007/085508
申请日：2007-11-26
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C. , LOUVEL, Jean-Paul
发明人： LOUVEL, Jean-Paul
IPC分类号： H05B41/282
CPC分类号： H05B41/2822 , H05B41/2827
摘要： A lighting system comprising a first plurality of fluorescent lamps (17) constituted by a first and a second lamp (20, 21) having a first common terminal (18) which is connected via a first capacitor (22) to a first terminal (12) of a voltage source (11). The system further comprises a second plurality of fluorescent lamps (29) constituted by a third and a fourth lamp (32, 33) having a first common terminal (30) which is connected via a second capacitor (34) to the first terminal (12) of a voltage source (11). The second terminals of the first lamp (20) and third lamp (32) are connected to a first terminal (24) of a third capacitor (25), said third capacitor (25) being connected with its second terminal to the second terminal (13) of the voltage source (11). The second terminals of the second lamp (21) and fourth lamp (33) are connected to a first terminal (36) of a fourth capacitor (37), the fourth capacitor (37) being connected with its second terminal to the second terminal (13) of the voltage source (11).
摘要翻译：一种照明系统，包括由具有第一公共端子（18）的第一和第二灯（20,21）构成的第一多个荧光灯（17），所述第一公共端子（18）经由第一电容器（22）连接到第一端子（12））电压源（11）。该系统还包括由具有第一公共端子（30）的第三和第四灯（32,33）构成的第二多个荧光灯（29），第一公共端子（30）经由第二电容器（34）连接到第一端子）电压源（11）。第一灯（20）和第三灯（32）的第二端子连接到第三电容器（25）的第一端子（24），所述第三电容器（25）与其第二端子连接到第二端子 13）。第二灯（21）和第四灯（33）的第二端子连接到第四电容器（37）的第一端子（36），第四电容器（37）与其第二端子连接到第二端子 13）。

26. 发明申请

WO2008013531A1 AMPLIFICATION CIRCUIT AND METHOD THEREFOR 审中-公开
标题翻译：放大电路及其方法
公开(公告)号：WO2008013531A1
公开(公告)日：2008-01-31
申请号：PCT/US2006/028987
申请日：2006-07-25
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C. , PUJOL, Alexandre , RAMOND, Stephane
发明人： PUJOL, Alexandre , RAMOND, Stephane
IPC分类号： H03F1/30 , H03F3/181 , H03F3/45 , H03F3/72
CPC分类号： H03F1/305 , H03F3/181 , H03F3/45475 , H03F3/72 , H03F2200/03 , H03F2200/421 , H03F2203/45138
摘要： In one embodiment, an amplification circuit charges a filter capacitor (14) and an input capacitor (12) with a substantially constant current and subsequently forms a delay prior to operating the amplification circuit to amplify input signals.
摘要翻译：在一个实施例中，放大电路以基本恒定的电流对滤波电容器（14）和输入电容器（12）充电，并且随后在操作放大电路以放大输入信号之前形成延迟。

27. 发明申请

WO2007120131A1 METHOD FOR REGULATING A VOLTAGE AND CIRCUIT THEREFOR 审中-公开
标题翻译：用于调节其电压和电路的方法
公开(公告)号：WO2007120131A1
公开(公告)日：2007-10-25
申请号：PCT/US2006/014299
申请日：2006-04-18
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C. , TURCHI, Joel , BASSO, Christophe
发明人： TURCHI, Joel , BASSO, Christophe
IPC分类号： H02M3/156
CPC分类号： H02M1/4225 , H02M2001/0025 , Y02B70/126
摘要： A regulator circuit and a method for regulating an output voltage. The regulator circuit includes an undervoltage protection stage capable of operating in a plurality of operating modes. In one mode, the undervoltage protection stage compensates for a low undervoltage appearing in the output voltage and in another mode it compensates for a large undervoltage appearing in the output voltage. When the output voltage has a low undervoltage, a portion of the current from a current source is routed to a feedback network to balance the input voltages of the undervoltage protection stage and to place the voltage regulator in a steady state operating mode. When the output voltage has a large undervoltage, the undervoltage protection stage turns on a current sourcing transistor that cooperates with the current from the current source to quickly charge a compensation capacitor and increase the power appearing at the output of the voltage regulator.
摘要翻译：调节器电路和调节输出电压的方法。调节器电路包括能够以多种操作模式操作的欠压保护级。在一种模式中，欠压保护级补偿输出电压中出现的低欠压，而在另一种模式下，补偿输出电压中出现的大的欠压。当输出电压具有低欠压时，来自电流源的电流的一部分被路由到反馈网络以平衡欠压保护级的输入电压并将电压调节器置于稳态操作模式。当输出电压具有较大的欠压时，欠压保护级接通电流源晶体管，其与来自电流源的电流配合，从而对补偿电容器进行快速充电，并增加出现在电压调节器输出端的功率。

28. 发明申请

WO2007100327A1 METHOD FOR REGULATING A VOLTAGE AND CIRCUIT THEREFOR 审中-公开
标题翻译：用于调节其电压和电路的方法
公开(公告)号：WO2007100327A1
公开(公告)日：2007-09-07
申请号：PCT/US2006/007449
申请日：2006-03-02
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C. , TURCHI, Joel , BASSO, Christophe
发明人： TURCHI, Joel , BASSO, Christophe
IPC分类号： H02M1/00 , H02H7/12
CPC分类号： H02H7/1216
摘要： A voltage regulator having an overload protection circuit and a method for protecting against an output voltage being less than a predetermined level. The voltage regulator has an overload protection circuit coupled between a feedback network and a regulation section. A power factor correction circuit is connected to the regulation section. An output voltage from the power factor correction circuit is fed back to the feedback network, which transmits a portion of the output voltage to the overload protection circuit. If the output voltage is less than the predetermined voltage level, a transconductance amplifier generates a current that sets an overload flag. Setting the overload flag initiates a delay timer. If the delay exceeds a predetermined amount of time, the overload protection circuit shuts down the voltage regulator.
摘要翻译：具有过载保护电路的电压调节器和用于防止小于预定电平的输出电压的方法。电压调节器具有耦合在反馈网络和调节部分之间的过载保护电路。功率因数校正电路连接到调节部分。来自功率因数校正电路的输出电压被反馈到反馈网络，反馈网络将输出电压的一部分传送到过载保护电路。如果输出电压小于预定电压电平，则跨导放大器产生设定过载标志的电流。设置过载标志启动延迟定时器。如果延迟超过预定的时间，则过载保护电路关闭稳压器。

29. 发明申请

WO2007084134A1 COMMUNICATION CIRCUIT AND METHOD THEREFOR 审中-公开
标题翻译：通信电路及其方法
公开(公告)号：WO2007084134A1
公开(公告)日：2007-07-26
申请号：PCT/US2006/002359
申请日：2006-01-23
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C. , BAIRANZADE, Michael , CHAOUI, Hassan , GENEST, Pierre Andre
发明人： BAIRANZADE, Michael , CHAOUI, Hassan , GENEST, Pierre Andre
IPC分类号： H04L7/06 , G06F13/42 , H03M7/40
CPC分类号： H03M7/40 , H03M5/16 , H04L69/03 , H04L69/06
摘要： In one embodiment, a circuit is configured to operate with a communication protocol that has at least three different signal levels wherein different sequences of the three levels identify different elements of the communication protocol. In another embodiment, a modular control block may be used to select the communication protocol and the operation of the circuit.
摘要翻译：在一个实施例中，电路被配置为使用具有至少三个不同信号电平的通信协议进行操作，其中三个电平的不同序列标识通信协议的不同元件。在另一个实施例中，可以使用模块化控制块来选择通信协议和电路的操作。

30. 发明申请

WO2006068642A1 SEMICONDUCTOR PACKAGE STRUCTURE HAVING ENHANCED THERMAL DISSIPATION CHARACTERISTICS 审中-公开
标题翻译：具有增强热释放特性的半导体封装结构
公开(公告)号：WO2006068642A1
公开(公告)日：2006-06-29
申请号：PCT/US2004/043076
申请日：2004-12-20
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C. , CARNEY, Francis J. , SEDDON, Michael J.
发明人： CARNEY, Francis J. , SEDDON, Michael J.
IPC分类号： H01L23/495 , H01L23/31
CPC分类号： H01L23/49562 , H01L23/3107 , H01L23/49524 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/05624 , H01L2224/37124 , H01L2224/37139 , H01L2224/37144 , H01L2224/37147 , H01L2224/37164 , H01L2224/37639 , H01L2224/4007 , H01L2224/40095 , H01L2224/40245 , H01L2224/4103 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48624 , H01L2224/48724 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： In one embodiment, a packaged semiconductor device having enhanced thermal dissipation characteristics includes a lead frame structure and a semiconductor chip having a major current carrying or heat generating electrode. The semiconductor chip is oriented so that the major current carrying electrode faces the top of the package or away from the next level of assembly. The packaged semiconductor device further includes a non-planar, stepped or undulating attachment structure coupling the current carrying electrode to the lead frame. A high thermal conductivity mold compound and thin package profile further enhance thermal dissipation.
摘要翻译：在一个实施例中，具有增强的散热特性的封装半导体器件包括引线框架结构和具有主要载流或发热电极的半导体芯片。半导体芯片被定向成使得主载流电极面向封装的顶部或远离下一级组件。封装的半导体器件还包括将载流电极耦合到引线框架的非平面，阶梯状或起伏的附接结构。高导热性模具化合物和薄封装外形进一步增强散热性能。

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