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21. 发明申请

WO2013070437A1 ADSORPTION SITE BLOCKING METHOD FOR CO-DOPING ALD FILMS 审中-公开
标题翻译：用于混合ALD膜的吸附位点阻断方法
公开(公告)号：WO2013070437A1
公开(公告)日：2013-05-16
申请号：PCT/US2012/061731
申请日：2012-10-24
申请人： INTERMOLECULAR, INC. , ELPIDA MEMORY, INC.
发明人： MALHOTRA, Sandra , CHEN, Hanhong , DEWEERD, Wim , HIROTA, Toshiyuki , ODE, Hiroyuki
IPC分类号： H01L21/31
CPC分类号： H01L28/60 , C23C16/45534 , H01L21/02175 , H01L21/02178 , H01L21/02186 , H01L21/02189 , H01L21/02194 , H01L21/0228 , H01L27/10852 , H01L28/40 , H01L28/56 , H01L29/4234
摘要： A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.
摘要翻译：一种用于通过脉冲第一掺杂剂前体掺杂电介质材料的方法，清洗未吸附的前体，脉冲第二前体，净化未吸附的前体，以及脉冲氧化剂以形成两个（或多个）金属氧化物的混合层电介质掺杂剂材料。该方法还可用于在体电介质层和第二电极层之间形成阻挡层。该方法改善了组合物的控制和掺杂介质材料整个厚度均匀性的控制。

22. 发明专利

DE102008031511A1 未知
公开(公告)号：DE102008031511A1
公开(公告)日：2009-04-23
申请号：DE102008031511
申请日：2008-07-03
申请人： ELPIDA MEMORY INC
发明人： WATANABE MITSUHISA , ANJOH ICHIRO
IPC分类号： H01L23/32 , H01L21/58 , H01L21/78
摘要： A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 mum or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.

23. 发明专利

DE69936611D1 未知
公开(公告)号：DE69936611D1
公开(公告)日：2007-09-06
申请号：DE69936611
申请日：1999-05-19
申请人： ELPIDA MEMORY INC
发明人： SHIBATA KAYOKO
IPC分类号： G11C7/00 , G11C11/41 , G11C7/10 , G11C11/407 , G11C11/409
摘要： The present invention provides a circuitry for supplying data from a write input/output line pair to a digit line pair for writing the data into memory cells. The circuitry comprises : a balancing device for balancing in voltage level between the write input/output line pair by making a connection of the write input/output line pair ; and a controller connected to the balancing device for controlling balancing operations of the balancing device.

24. 发明专利

DE10107427B4 未知
公开(公告)号：DE10107427B4
公开(公告)日：2007-06-14
申请号：DE10107427
申请日：2001-02-16
申请人： ELPIDA MEMORY INC
发明人： MATSUI YOSHINORI , IKEDA HIROAKI
IPC分类号： G11C29/00 , G11C29/04 , G06F12/08 , G11C8/00 , G11C8/10 , G11C29/44
摘要： A semiconductor memory device, that uses redundant memory cell clusters sharing one data transfer bus line to perform defect recovery for a plurality of defects, and provides an improved rate of recovery. The semiconductor memory device is formed from a main memory, a sub-memory functioning as cache memory, and a plurality of data transfer bus lines, which are configured so that data can be transferred bi-directionally between said main memory and said sub-memory; and performs defect recovery for defects located in said main memory based on an address signal (sub-memory column selecting signal SYm) for said sub-memory and address signals (main memory row selecting signal DXn and bank selecting signal BS) in said main memory, which correspond to said address.

25. 发明专利

DE10239515B4 未知
公开(公告)号：DE10239515B4
公开(公告)日：2007-05-10
申请号：DE10239515
申请日：2002-08-28
申请人： ELPIDA MEMORY INC
发明人： HASHIMOTO TAKESHI , ITO YUTAKA
IPC分类号： G11C11/407 , G11C11/401 , G11C11/4074 , G11C11/403 , G11C11/406
摘要： In a semiconductor memory device which requires a refresh operation, a control method stops supplying a word line voltage which is a boosted voltage higher than an external supply voltage, a memory array substrate voltage which is a negative voltage supplied to a semiconductor substrate, and a bit line precharge voltage for use in reproducing data held in memory cells for a predetermined period at the end of each refresh operation. In this event, voltage output terminals of the word line and memory array substrate voltages are respectively driven to a ground potential. For recovering these voltages, the delivery of the word line voltage is stopped until the memory array substrate voltage rises to some extent.

26. 发明专利

DE102006024455A1 未知
公开(公告)号：DE102006024455A1
公开(公告)日：2007-01-11
申请号：DE102006024455
申请日：2006-05-24
申请人： ELPIDA MEMORY INC
发明人： IKEDA HIROAKI , SASAKI MAMORU , IWATA ATSUSHI
IPC分类号： G11C5/02
摘要： Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circuit is formed for the memory cell. The plurality of core chips through have latch circuit units through for temporarily storing data to be outputted by the memory cell, and latch circuit units through for temporarily storing data to be inputted to the memory cell, respectively, and these latch circuit units through and latch circuit units through are connected in a cascade to the interface chip. Since the plurality of latch circuit units connected in a cascade can thereby perform a pipeline operation, it becomes possible to achieve high-speed data transfer.

27. 发明专利

DE102005013885A1 未知
公开(公告)号：DE102005013885A1
公开(公告)日：2005-12-15
申请号：DE102005013885
申请日：2005-03-24
申请人： ELPIDA MEMORY INC
发明人： OYU KIYONORI , OKONOGI KENSUKE , KOBAYASHI HIROTAKA , HAMADA KOJI
IPC分类号： H01L21/322 , H01L21/02 , H01L21/302 , H01L21/304 , H01L21/461 , H01L21/50
摘要： In manufacturing a semiconductor device, the first gettering layer is formed on the backside of a wafer, and the second gettering layers are then formed on the backside and side surfaces of a chip, allowing these gettering layers to serve as trapping sites against metallic contamination that generated after backside grinding in assembly processes.

28. 发明专利

DE102004036455A1 未知
公开(公告)号：DE102004036455A1
公开(公告)日：2005-05-12
申请号：DE102004036455
申请日：2004-07-28
申请人： ELPIDA MEMORY INC
发明人： TAKAI YASUHIRO , KOBAYASHI SHOTARO
IPC分类号： G06F1/10 , G11C11/407 , G11C11/4076 , H03K5/04 , H03K5/13 , H03L7/081 , H03L7/087 , H03K5/14
摘要： A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

29. 发明专利

DE10346945A1 Slew-rate control system for synchronous dynamic random access memory, changes output data or transition speed based on signal which shows variation in electrical potential difference 未知
公开(公告)号：DE10346945A1
公开(公告)日：2004-05-27
申请号：DE10346945
申请日：2003-10-09
申请人： ELPIDA MEMORY INC
发明人： SHIBATA TOMOYUKI , OISHI KANJI
IPC分类号： H03K5/12 , G11C11/409 , H03K17/687 , H03K19/003 , H03K19/0175
摘要： Electrical potential difference of two power supply sources are sampled at a predetermined time and a signal is generated which describes electrical-potential difference variation. The change of transition speed or output data of output buffer circuit (4) is performed according to generated signal.

30. 发明专利

DE10334531A1 未知
公开(公告)号：DE10334531A1
公开(公告)日：2004-03-25
申请号：DE10334531
申请日：2003-07-29
申请人： ELPIDA MEMORY INC
发明人： SHIBATA KAYOKO , NISHIO YOJI , FUNABA SEIJI
IPC分类号： G06F13/16 , G06F12/00 , G11C11/4063 , H05K1/02 , G06F13/00
摘要： A memory module comprises a stab resistor between a pin and one end of a bus. A plurality of memory chips is connected to the bus between both ends thereof. A terminating resistor is connected to the other end of the bus. Stab resistance Rs of the stab resistor and terminating resistance Rterm of the terminating resistor are given by: Rs=(N-1)xZeffdimm/N, and Rterm=Zeffdimm where N represents the number of the memory modules in a memory system; and Zeffdimm, effective impedance of a memory chip arrangement portion consisting of the bus and the memory chips. In the memory system, the memory modules are connected to a memory controller on a motherboard in a stab connection style. Wiring impedance Zmb of the motherboard is given by: Zmb=(2N-1)xZeffdimm/N 2 .

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