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21. 发明申请

US20100295661A1 Random Delay Generation for Thin-Film Transistor Based Circuits 有权
标题翻译：基于薄膜晶体管的电路的随机延迟生成
公开(公告)号：US20100295661A1
公开(公告)日：2010-11-25
申请号：US12625435
申请日：2009-11-24
申请人： Vivek SUBRAMANIAN , Mingming Mao , Zhigang Wang
发明人： Vivek SUBRAMANIAN , Mingming Mao , Zhigang Wang
IPC分类号： H04B7/24 , H04B1/04 , H03K3/36 , H03B5/12
CPC分类号： H04B1/04 , G06K7/0008 , G06K7/10059 , G06K19/0723 , H01L22/20 , H01L2924/0002 , H03B5/1203 , H03K3/0315 , H03K3/033 , H03K3/355 , H03K5/13 , H03K5/133 , H04H20/16 , H01L2924/00
摘要： Circuits and circuit elements configured to generate a random delay, a monostable oscillator, circuits configured to broadcasting repetitive messages wireless systems, and methods for forming such circuits, devices, and systems are disclosed. The present invention advantageously provides relatively low cost delay generating circuitry based on TFT technology in wireless electronics applications, particularly in RFID applications. Such novel, technically simplified, low cost TFT-based delay generating circuitry enables novel wireless circuits, devices and systems, and methods for producing such circuits, devices and systems.
摘要翻译：被配置为产生随机延迟的电路和电路元件，单稳态振荡器，被配置为广播重复消息无线系统的电路，以及用于形成这种电路，装置和系统的方法。本发明有利地提供了在无线电子应用中特别是RFID应用中基于TFT技术的相对较低成本的延迟产生电路。这种新颖的，技术上简化的，低成本的基于TFT的延迟产生电路实现了新颖的无线电路，设备和系统以及用于生产这样的电路，设备和系统的方法。

22. 发明授权

US07758083B2 Wall bushing for air conditioner 失效
标题翻译：空调墙壁套管
公开(公告)号：US07758083B2
公开(公告)日：2010-07-20
申请号：US11911790
申请日：2006-04-13
申请人： Boyang Ni , Zhigang Wang , Deyong Fang
发明人： Boyang Ni , Zhigang Wang , Deyong Fang
IPC分类号： F16L3/00
CPC分类号： F24F1/025 , F16L5/00 , F24F2007/001 , Y10S285/901
摘要： A wall bushing for an air-conditioner comprises an external pipe and an internal pipe. The cross section of the external pipe is a “sports ground” shape, and an inner circular wall of the external pipe is tangential to an outer circular wall of the internal pipe. An end of the internal pipe is connected to an air outlet port of the air conditioner, and an end of the external pipe is connected to an air inlet port.
摘要翻译：用于空调的壁套管包括外管和内管。外管的横截面是“运动场”形状，外管的内圆壁与内管的外圆壁相切。内管的一端连接到空调的出风口，外管的一端与进气口连接。

23. 发明授权

US07697330B1 Non-volatile memory array having drain-side segmentation for an FPGA device 有权
标题翻译：具有用于FPGA器件的漏极侧分割的非易失性存储器阵列
公开(公告)号：US07697330B1
公开(公告)日：2010-04-13
申请号：US11961203
申请日：2007-12-20
申请人： Vidyahara Bellippady , Santosh Yachareni , Fethi Dhaoui , Zhigang Wang
发明人： Vidyahara Bellippady , Santosh Yachareni , Fethi Dhaoui , Zhigang Wang
IPC分类号： G11C16/00
CPC分类号： G11C16/0441
摘要： A non-volatile memory array for an FPGA comprises a plurality of memory cells arranged in rows and columns and divided into a plurality of row segments. The source of each non-volatile memory transistor in each segment is coupled together to a common source line. A column segment line is associated with each segment of the array, and is coupled to the drains of each non-volatile memory transistor in the segment. A segment select transistor is coupled between each column segment line and its associated column line, and a high-voltage driver transistor is coupled to each column line.
摘要翻译：用于FPGA的非易失性存储器阵列包括以行和列排列并分成多个行段的多个存储单元。每个段中的每个非易失性存储器晶体管的源极耦合到一个共同的源极线。列分段线与阵列的每个段相关联，并且被耦合到段中的每个非易失性存储器晶体管的漏极。段选择晶体管耦合在每个列分段线与其相关联的列线之间，并且高电压驱动晶体管耦合到每个列线。

24. 发明申请

US20070130553A1 Analog layout module generator and method 有权
标题翻译：模拟布局模块发生器和方法
公开(公告)号：US20070130553A1
公开(公告)日：2007-06-07
申请号：US11295268
申请日：2005-12-06
申请人： Zhigang Wang , Elias Fallon , Regis Colwell
发明人： Zhigang Wang , Elias Fallon , Regis Colwell
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5063
摘要： In a computer implemented method of device layout in an integrated circuit design an array having a plurality of cells is selected and stored in a memory of a computer. A schematic view of a plurality of interconnected circuit devices of a circuit is displayed on the computer's display. One or more of the circuit devices of the displayed schematic view are selected by a user. Responsive to the selection of each circuit device, a processing means of the computer populates an empty cell of the array in the memory of the computer with a corresponding layout instance of the circuit device, wherein each layout instance represents a physical arrangement of material(s) that form the corresponding selected circuit device.
摘要翻译：在集成电路设计中的设备布局的计算机实现方法中，选择具有多个单元的阵列并将其存储在计算机的存储器中。在计算机的显示器上显示电路的多个互连电路装置的示意图。所显示的示意图的一个或多个电路装置由用户选择。响应于每个电路装置的选择，计算机的处理装置用电路装置的相应布局实例填充计算机的存储器中的阵列的空单元，其中每个布局实例表示材料的物理布置），形成相应的所选择的电路装置。

25. 发明授权

US07042767B2 Flash memory unit and method of programming a flash memory device 有权
公开(公告)号：US07042767B2
公开(公告)日：2006-05-09
申请号：US10909693
申请日：2004-08-02
申请人： Zhigang Wang , Nian Yang , Zhizheng Liu
发明人： Zhigang Wang , Nian Yang , Zhizheng Liu
IPC分类号： G11C16/04
CPC分类号： G11C16/12
摘要： Disclosed are a flash memory unit and a method of programming a flash memory device. The method of programming can include applying respective programming voltages to a control gate and a drain of the memory device. A source bias potential can be applied to a source of the memory device. The application of the source bias potential can be controlled with the selective application of one of the programming voltages to a source bias switching device.

26. 发明授权

US07042766B1 Method of programming a flash memory device using multilevel charge storage 有权
标题翻译：使用多电平电荷存储来编程闪存器件的方法
公开(公告)号：US07042766B1
公开(公告)日：2006-05-09
申请号：US10896651
申请日：2004-07-22
申请人： Zhigang Wang , Nian Yang , Zhizheng Liu
发明人： Zhigang Wang , Nian Yang , Zhizheng Liu
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/12 , G11C16/3468 , G11C2211/5621
摘要： Disclosed is a method of programming a flash memory device to store an amount of charge corresponding to one of a plurality of charged program states. The method can include pulsing the memory device with program voltages including at least a gate voltage. If the gate voltage is greater than or equal to a predetermined minimum threshold voltage for the one of the plurality of charged program states, an amount of charge stored by the memory device can be verified. Otherwise the memory device can be repulsed. This procedure can be carried out until verifying is conducted and the verifying indicates that the amount of charge stored by the memory device corresponds to the one of the plurality of charged program states.
摘要翻译：公开了一种编程闪速存储器件以存储对应于多个充电程序状态之一的电荷量的方法。该方法可以包括使具有至少包括栅极电压的编程电压脉冲存储器件。如果栅极电压大于或等于多个充电程序状态之一的预定最小阈值电压，则可以验证由存储器件存储的电荷量。否则可能会使存储器件发生故障。可以执行该过程，直到进行验证，并且验证指示存储器件存储的电荷量对应于多个充电程序状态中的一个。

27. 发明授权

US07020022B1 Method of reference cell design for optimized memory circuit yield 失效
标题翻译：参考电池设计方法优化了存储器电路的产量
公开(公告)号：US07020022B1
公开(公告)日：2006-03-28
申请号：US10887782
申请日：2004-07-09
申请人： John Wang , Zhigang Wang , Xin Guo
发明人： John Wang , Zhigang Wang , Xin Guo
IPC分类号： G11C16/00
CPC分类号： G11C16/28
摘要： A method for standard reference cell design is herein disclosed. The method includes determining a first number of individual bits to be employed in a standard reference cell design based on the number of individual bits that are included in core memory cells that are to be measured using the standard reference cell. The method further includes determining a range of variation in the core memory cells to be measured that is due to process variation in the generation of the core memory cells. In addition, the method includes determining an additional number of individual bits to be included in the standard reference cell design based on the determined range of variation. A standard reference cell that includes a number of individual bits equal to the sum of both the first and the additional number of individual bits is generated.
摘要翻译：本文公开了一种用于标准参考电池设计的方法。该方法包括基于使用标准参考小区来测量的核心存储器单元中包含的各个比特的数量来确定在标准参考小区设计中采用的单个比特的第一数量。该方法还包括确定由于核心存储器单元的产生中的过程变化而导致的要测量的核心存储器单元的变化范围。此外，该方法包括基于所确定的变化范围来确定要包括在标准参考单元设计中的附加数量的单独位。生成包括等于第一个和另外个数的个数之和的个别位数的标准参考单元。

28. 发明授权

US06867323B2 Cross-coupling reaction of organosilicon nucleophiles 有权
标题翻译：有机硅亲核试剂的交叉偶联反应
公开(公告)号：US06867323B2
公开(公告)日：2005-03-15
申请号：US09875777
申请日：2001-06-06
申请人： Scott E. Denmark , Jun Young Choi , Daniel Wehrli , Zhicai Wu , Luc Neuville , Weitao Pan , Ramzi F. Sweis , Zhigang Wang , Shyh-Ming Yang
发明人： Scott E. Denmark , Jun Young Choi , Daniel Wehrli , Zhicai Wu , Luc Neuville , Weitao Pan , Ramzi F. Sweis , Zhigang Wang , Shyh-Ming Yang
IPC分类号： C07B37/04 , C07C1/32 , C07C29/36 , C07C29/44 , C07C41/30 , C07C45/68 , C07C45/72 , C07C67/343 , C07C205/06 , C07F7/08 , C07F7/12 , C07F7/18 , C07F7/21 , C07C67/00
CPC分类号： C07C29/36 , C07B37/04 , C07C1/325 , C07C29/44 , C07C41/30 , C07C45/68 , C07C45/72 , C07C67/343 , C07C201/12 , C07C2527/13 , C07C2531/22 , C07F7/0827 , C07F7/083 , C07F7/0836 , C07F7/0838 , C07F7/0896 , C07F7/12 , C07F7/1804 , C07F7/21 , C07C33/28 , C07C33/30 , C07C33/02 , C07C49/835 , C07C49/796 , C07C49/794 , C07C69/76 , C07C205/06 , C07C205/19 , C07C205/35 , C07C43/215 , C07C43/15 , C07C43/225 , C07C43/23 , C07C43/164
摘要： Improved methods for generating a —C—C— bond by cross-coupling of a transferable group with an acceptor group. The transferable group is a substituent of an organosilicon nucleophile and the acceptor group is provided as an organic electrophile. The reaction is catalyzed by a Group 10 transition metal complex (e.g., Ni, Pt or Pd), particularly by a palladium complex. Certain methods of this invention use improved organosilicon nucleophiles which are readily prepared, can give high product yields and exhibit high stereoselectivity. Methods of this invention employ activating ions such as halides, hydroxide, hydride and silyloxides. In specific embodiments, organosilicon nucleophilic reagents of this invention include siloxanes, particularly cyclic siloxanes. The combination of the cross-coupling reactions of this invention with ring-closing metathesis, hydrosilylation and intramolecular hydrosilylation reactions provide useful synthetic strategies that have wide application.
摘要翻译：通过可转移基团与受体基团的交叉偶联产生-C-C键的改进方法。可转移基团是有机硅亲核试剂的取代基，并且受体基团作为有机亲电试剂提供。该反应由第10族过渡金属络合物（例如，Ni，Pt或Pd）催化，特别是由钯络合物催化。本发明的某些方法使用易于制备的改进的有机硅亲核试剂，可以提供高产物产率并显示高立体选择性。本发明的方法使用活化离子如卤化物，氢氧化物，氢化物和甲硅烷氧基。在具体实施方案中，本发明的有机硅亲核试剂包括硅氧烷，特别是环状硅氧烷。本发明的交叉偶联反应与闭环复分解，氢化硅烷化和分子内氢化硅烷化反应的组合提供了广泛应用的有用的合成策略。

29. 发明授权

US06818462B1 METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A C-V MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND A DEVICE THEREBY FORMED 失效
标题翻译：使用C-V测量技术确定闪存隔离结构之间的活性区域宽度的方法，用于制造闪速存储器半导体器件及其形成的器件
公开(公告)号：US06818462B1
公开(公告)日：2004-11-16
申请号：US10224028
申请日：2002-08-19
申请人： Tien-Chun Yang , Nian Yang , Zhigang Wang
发明人： Tien-Chun Yang , Nian Yang , Zhigang Wang
IPC分类号： H01L2166
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method of determining the active region width (10) of an active region (4) by measuring the respective capacitance values (C100, C100′, C100″) of respective composite capacitance structures (100, 100′, 100″), respectively comprising at least one capacitor element(16, 17, 18; 16′, 17′, 18″; 16″, 17″, 18″) having respective predetermined widths (Wi) for fabricating a flash memory semiconductor device, and a device thereby fabricated. The present method also comprises plotting the respective capacitance values (C100, C100′, C100″) as a quasi-linear function (CW) of the respective predetermined widths (Wi), extrapolating a calibration term (WC=0) from the quasi-linear function (CW), and subtracting the calibration term (WC=0) from the respective predetermined widths (Wi) to define and constrain the active region width (10) for facilitating device fabrication.
摘要翻译：通过测量各个复合电容结构（100,100'，100“）的各个电容值（C100，C100'，C100”）来确定有源区域（4）的有源区宽度（10）的方法，分别包括至少一个电容器元件（16,17,18; 16'，17“，18”，16“，17”，18“），其具有用于制造闪速存储器半导体器件的各自的预定宽度，以及由此制造的装置。本方法还包括将各个电容值（C100，C100'，C100“）绘制为各个预定宽度（Wi）的准线性函数（CW），从准准则中外推校准项（WC = 0）线性函数（CW），并从相应的预定宽度（Wi）减去校准项（WC = 0），以限定和约束有源区宽度（10）以便于器件制造。

30. 发明授权

US06717850B1 Efficient method to detect process induced defects in the gate stack of flash memory devices 失效
标题翻译：高效的方法来检测闪存器件的栅极堆叠中的工艺引起的缺陷
公开(公告)号：US06717850B1
公开(公告)日：2004-04-06
申请号：US10313676
申请日：2002-12-05
申请人： Jiang Li , Nian Yang , Zhigang Wang , John Jianshi Wang
发明人： Jiang Li , Nian Yang , Zhigang Wang , John Jianshi Wang
IPC分类号： G11C1604
CPC分类号： G11C29/50 , G11C16/04 , G11C2029/0403
摘要： A method of processing a semiconductor device is disclosed and comprises applying a relatively high voltage across a gate stack of a flash memory cell for a certain period of time. Then, the polarity of the applied voltage is reversed and is again applied across the gate stack for another certain period of time. The voltage applied is greater than a channel erase voltage utilized for the memory cell. This applied voltage causes extrinsic defects to become amplified at interfaces of oxide/insulator layers of the gate stack. Then, the memory cell is tested (e.g., via a battery of tests) in order to determine if the memory cell is defective. If the cell is defective (e.g., fails the test), it can be assumed that substantial extrinsic defects were present in the memory cell and have been amplified resulting in the test failure. If the cell passes the test, it can be assumed that the memory cell is substantially free from extrinsic defects. Defective memory cells/devices can be marked or otherwise indicated as being defective.
摘要翻译：公开了一种处理半导体器件的方法，并且包括在闪存单元的栅极堆叠上施加相当高的电压一段时间。然后，施加的电压的极性反转，并再次施加在栅极堆叠另外一段时间。施加的电压大于用于存储器单元的通道擦除电压。该施加的电压导致外部缺陷在栅极堆叠的氧化物/绝缘体层的界面处被放大。然后，测试存储器单元（例如，通过测试电池），以便确定存储器单元是否有故障。如果细胞有缺陷（例如，测试失败），则可以认为在存储单元中存在大量的外在缺陷并且被放大，导致测试失败。如果单元通过测试，则可以认为存储单元基本上没有外在缺陷。存储器单元/器件不良或可能被标记为有缺陷。

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