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21. 发明申请

WO2020237627A1 SPEAKER ADAPTER, AND DUAL CORE SPEAKER ASSEMBLY 审中-公开
公开(公告)号：WO2020237627A1
公开(公告)日：2020-12-03
申请号：PCT/CN2019/089537
申请日：2019-05-31
申请人： HARMAN INTERNATIONAL INDUSTRIES, INCORPORATED , SUN, Bo
发明人： SUN, Bo , WANG, Jian , CHEN, Cathy , LIU, Na
IPC分类号： H04R1/20
摘要： The present disclosure provides a speaker adapter, and a dual core speaker assembly. The speaker adapter includes: a main body, symmetrically provided with two mounting portions at both sides for matching with speakers respectively; a bottom base, extending from and around the main body, for supporting the main body from bottom; and an inner cavity formed within the main body.

22. 发明申请

WO2011084527A3 SIGNAL DECIMATION TECHNIQUES BASED ON A CONFIGURABLE FREQUENCY DIVIDER AND A CONFIGURABLE DELAY 审中-公开
公开(公告)号：WO2011084527A3
公开(公告)日：2011-07-14
申请号：PCT/US2010/060585
申请日：2010-12-15
申请人： QUALCOMM INCORPORATED , BALLANTYNE, Gary John , GENG, Jifeng , SUN, Bo
发明人： BALLANTYNE, Gary John , GENG, Jifeng , SUN, Bo
IPC分类号： H03B19/00 , H03D7/16 , G06F1/08 , H03L7/00 , H04B1/00
摘要： Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.

23. 发明申请

WO2011028614A2 SYSTEM AND METHOD FOR AMPLIFYING A SIGNAL USING MULTIPLE AMPLIFICATION STAGES SHARING A COMMON BIAS CURRENT 审中-公开
标题翻译：使用多个扩展阶段放大信号的系统和方法共享公共偏置电流
公开(公告)号：WO2011028614A2
公开(公告)日：2011-03-10
申请号：PCT/US2010/046827
申请日：2010-08-26
申请人： QUALCOMM INCORPORATED , SUN, Bo , SEGORIA, Anthony, F.
发明人： SUN, Bo , SEGORIA, Anthony, F.
IPC分类号： H03F1/30 , H03F3/191 , H03F3/45
CPC分类号： H03F1/301 , H03F1/0283 , H03F3/191 , H03F3/45183 , H03F2203/45544 , H03F2203/45562 , H03F2203/45652 , H04B2001/6908
摘要： An apparatus including cascaded amplification stages adapted to be biased by a common DC current to generate an amplified output signal from an input signal. A first amplification stage includes a routing network to substantially double an input voltage signal, and a first transconductance gain stage to generate a first current signal from the input voltage signal. A second amplification stage includes a resonator to convert the first current signal into a second voltage signal, and a second transconductance gain stage to generate a second current signal from the first current signal. A third amplification stage includes a current gain stage to generate a third current signal from the second current signal, and a load through which the third current signal flows to generate the output signal.
摘要翻译：一种包括级联放大级的装置，其适于被公共DC电流偏置以从输入信号产生放大的输出信号。第一放大级包括使输入电压信号基本上加倍的布线网络以及从输入电压信号产生第一电流信号的第一跨导增益级。第二放大级包括将第一电流信号转换成第二电压信号的谐振器和由第一电流信号产生第二电流信号的第二跨导增益级。第三放大级包括从第二电流信号产生第三电流信号的电流增益级和第三电流信号通过该负载产生输出信号的负载。

24. 发明申请

WO2010105031A2 WIDEBAND PHASE MODULATOR 审中-公开
标题翻译：宽带相位调制器
公开(公告)号：WO2010105031A2
公开(公告)日：2010-09-16
申请号：PCT/US2010/026941
申请日：2010-03-11
申请人： QUALCOMM INCORPORATED , SUN, Bo
发明人： SUN, Bo
IPC分类号： H04L27/20
CPC分类号： H04L27/2032 , H03C3/00 , H03L7/0812 , H04L27/205 , H04L27/361
摘要： An apparatus for phase modulation includes a delay locked loop configured to generate from a reference signal a plurality of phase shifted signals, each of the phase shifted signals being locked to the reference signal and having a different phase shift from the other phase shifted signals with respect to the reference signal, and a multiplexer configured to select one of the phase shifted signals.
摘要翻译：一种用于相位调制的装置包括：延迟锁定环路，被配置为从参考信号产生多个相移信号，每个相移信号被锁定到参考信号，并且与其它相移信号具有不同的相移以及被配置为选择所述相移信号之一的多路复用器。

25. 发明申请

WO2010062621A1 DIGITALLY CONTROLLED OSCILLATOR WITH IMPROVED DIGITAL FREQUENCY CALIBRATION 审中-公开
标题翻译：具有改进数字频率校准的数字控制振荡器
公开(公告)号：WO2010062621A1
公开(公告)日：2010-06-03
申请号：PCT/US2009/062258
申请日：2009-10-27
申请人： QUALCOMM Incorporated , SUN, Bo , YANG, Zixiang
发明人： SUN, Bo , YANG, Zixiang
IPC分类号： H03B5/08 , H03J3/06 , H03J3/20 , H03J5/02 , H03J7/04 , H03M1/10 , H03M1/86 , H03M1/68
CPC分类号： H03L7/099 , H03B5/1265 , H03J1/0008 , H03J2200/10 , H03L7/10 , H03L2207/06 , H03L2207/50 , H03M1/1019 , H03M1/1042 , H03M1/1047 , H03M1/682 , H03M1/86
摘要： Techniques for calibrating digitally controlled oscillators (DCOs) are disclosed. In one aspect of the disclosure, an initial set of control codes for operating the DCO with a coarse frequency tuning bank with multiple overlapping coarse frequency tuning segments (LTBs) and one fine main frequency tuning bank (MTB) is determined. A range of output frequencies produced from the initial set is identified. Instances of overlap are identified in the frequency range between consecutive LTB segments. An offset in the MTB is added that corresponds to the overlap instance between consecutive LTBs to establish a revised set. The revised control codes are utilized to tune the DCO over the desired frequency range.
摘要翻译：公开了用于校准数字控制振荡器（DCO）的技术。在本公开的一个方面，确定用于使用具有多个重叠粗调频调谐段（LTB）和一个精细主频调谐组（MTB）的粗调频调谐组操作DCO的初始控制码组。识别从初始集合产生的输出频率范围。在连续的LTB段之间的频率范围内识别重叠实例。添加MTB中的偏移量，其对应于连续LTB之间的重叠实例，以建立修订集。修改后的控制代码用于在期望的频率范围内调谐DCO。

26. 发明申请

WO2009152105A2 DYNAMIC CALIBRATION TECHNIQUES FOR DIGITALLY CONTROLLED OSCILLATOR 审中-公开
标题翻译：数字控制振荡器的动态校准技术
公开(公告)号：WO2009152105A2
公开(公告)日：2009-12-17
申请号：PCT/US2009/046642
申请日：2009-06-08
申请人： QUALCOMM INCORPORATED , SUN, Bo , BALLANTYNE, Gary John , RANGARAJAN, Rajagopalan
发明人： SUN, Bo , BALLANTYNE, Gary John , RANGARAJAN, Rajagopalan
IPC分类号： H03L7/099 , H04B1/04 , H04B1/16
CPC分类号： H03L7/099 , H03L2207/06
摘要： Techniques for calibrating digitally controlled oscillators (DCOs) are disclosed. In an aspect of the disclosure, an initial set of control codes for operating the DCO is determined. A range of output frequencies produced from the initial set is identified. Gaps or instances of overlap are identified in the frequency range. For the overlap case, control codes are removed from the initial set that correspond to the overlap instance to establish a revised set. For the gap case, control codes are added to the initial set for producing frequencies values that fill the gap. An apparatus for performing the same is also disclosed.
摘要翻译：公开了用于校准数字控制振荡器（DCO）的技术。在本公开的一方面，确定用于操作DCO的初始控制代码集。识别从初始集合产生的输出频率范围。在频率范围内识别重叠的间隙或实例。对于重叠情况，从与重叠实例相对应的初始集中移除控制代码以建立修订集。对于间隙情况，将控制代码添加到初始设置中，以产生填充间隙的频率值。还公开了一种用于执行该装置的装置。

27. 发明申请

WO2009111491A1 HIGH-SPEED TIME-TO-DIGITAL CONVERTER 审中-公开
标题翻译：高速时数转换器
公开(公告)号：WO2009111491A1
公开(公告)日：2009-09-11
申请号：PCT/US2009/035908
申请日：2009-03-03
申请人： QUALCOMM INCORPORATED , SUN, Bo , YANG, Zixiang
发明人： SUN, Bo , YANG, Zixiang
IPC分类号： H03M1/50
CPC分类号： G04F10/005
摘要： Techniques for enabling a time-to-digital converter (TDC) to sample with sub-inverter delay resolution are disclosed. In an embodiment, the inputs to a differential D-Q flip-flop in the TDC are coupled to a single-ended signal and a delayed and inverted version of that signal to allow time interpolation of the signal. Further disclosed are techniques to balance the loads of a first delay line and a complementary delay line within the TDC.
摘要翻译：公开了一种能够使时间数字转换器（TDC）采用次逆变器延迟分辨率进行采样的技术。在一个实施例中，TDC中的差分D-Q触发器的输入被耦合到单端信号和该信号的延迟和反相版本，以允许信号的时间插值。进一步公开的是平衡TDC内的第一延迟线和互补延迟线的负载的技术。

28. 发明申请

WO2009088790A1 DIGITAL PHASE-LOCKED LOOP WITH GATED TIME-TO-DIGITAL CONVERTER 审中-公开
标题翻译：数字锁相环与定位的时间到数字转换器
公开(公告)号：WO2009088790A1
公开(公告)日：2009-07-16
申请号：PCT/US2008/088263
申请日：2008-12-24
申请人： QUALCOMM Incorporated , SUN, Bo , SAHOTA, Gurkanwal Singh , YANG, Zixiang
发明人： SUN, Bo , SAHOTA, Gurkanwal Singh , YANG, Zixiang
IPC分类号： H03L7/08 , H03L7/087
CPC分类号： H03L7/0802 , H03L7/087
摘要： A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.
摘要翻译：数字PLL（DPLL）包括时间 - 数字转换器（TDC）和控制单元。定期启用TDC以持续短时间量化相位信息，并在剩余时间内禁用TDC以降低功耗。 TDC接收第一时钟信号和第一参考信号，并提供指示第一时钟信号和第一参考信号之间的相位差的TDC输出。控制单元基于主参考信号生成使能信号，并使能和禁止具有使能信号的TDC。在一种设计中，控制单元延迟主参考信号以获得第一参考信号和第二参考信号，基于主参考信号和第二参考信号产生使能信号，并且将主时钟信号与使能信号以获得TDC的第一个时钟信号。

29. 发明申请

WO2009073580A2 DIGITAL PHASE-LOCKED LOOP OPERATING BASED ON FRACTIONAL INPUT AND OUTPUT PHASES 审中-公开
标题翻译：基于分数输入和输出相位的数字锁相环操作
公开(公告)号：WO2009073580A2
公开(公告)日：2009-06-11
申请号：PCT/US2008/085084
申请日：2008-11-29
申请人： QUALCOMM INCORPORATED , BALLANTYNE, Gary John , SUN, Bo
发明人： BALLANTYNE, Gary John , SUN, Bo
IPC分类号： H03L7/085
CPC分类号： H03L7/10 , H03L7/085 , H03L7/087 , H03L2207/50
摘要： In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping tracking of the number of oscillator signal cycles based on the reference signal.
摘要翻译：在一个方面，数字PLL（DPLL）基于输入和输出相位的小数部分进行操作。 DPLL累加至少一个输入信号以获得输入相位。 DPLL基于来自振荡器的振荡器信号与参考信号之间的相位差（例如使用时间 - 数字转换器（TDC））来确定输出相位的小数部分。 DPLL根据输入相位的小数部分和输出相位的小数部分确定相位误差。 DPLL然后基于相位误差产生振荡器的控制信号。在另一方面，DPLL包括合成的累加器，其通过基于参考信号跟踪振荡器信号周期的数量来确定粗略的输出相位。

30. 发明申请

WO2009039444A1 MULTI-MODE AND MULTI-BAND TRANSMITTERS FOR WIRELESS COMMUNICATION 审中-公开
标题翻译：用于无线通信的多模和多带发射机
公开(公告)号：WO2009039444A1
公开(公告)日：2009-03-26
申请号：PCT/US2008/077121
申请日：2008-09-19
申请人： QUALCOMM INCORPORATED , SEE, Puay Hoe Andrew , SAHOTA, Gurkanwal Singh , SUN, Bo , BALLANTYNE, Gary, John , PANTON, William, Ronald , CHOI, Zae Yong
发明人： SEE, Puay Hoe Andrew , SAHOTA, Gurkanwal Singh , SUN, Bo , BALLANTYNE, Gary, John , PANTON, William, Ronald , CHOI, Zae Yong
IPC分类号： H04L27/00 , H04L27/36 , H04B1/00
CPC分类号： H04L27/0008 , H03C3/0916 , H03C3/0975 , H03C5/00 , H03F1/3241 , H03F1/3252 , H04B1/0483 , H04B2001/0425 , H04L27/361 , H04L27/362
摘要： Transmitters supporting multiple modulation modes and/or multiple frequency bands are described. A transmitter may perform large signal polar modulation, small signal polar modulation, and/or quadrature modulation, which may support different modulation schemes and systems. Circuit blocks may be shared by the different modulation modes to reduce cost and power. For example, a single modulator (160) and a single power amplifier (170) may be used for small signal polar modulation and quadrature modulation. The transmitter may apply pre-distortion (124,142) to improve performance, to allow a power amplifier to support multiple frequency bands, to allow the power amplifier to operate at higher output power levels, etc. Envelope and phase distortions due to non-linearity of the power amplifier may be characterized for different input levels and different bands and stored at the transmitter. Thereafter, envelope and phase signals may be pre-distorted based on the stored characterizations to compensate for non-linearity of the power amplifier.
摘要翻译：描述了支持多个调制模式和/或多个频带的发射机。发射机可以执行大信号极性调制，小信号极化调制和/或正交调制，其可以支持不同的调制方案和系统。电路块可以由不同的调制模式共享以降低成本和功率。例如，单个调制器（160）和单个功率放大器（170）可用于小信号极性调制和正交调制。发射机可以应用预失真（124,142）来提高性能，以允许功率放大器支持多个频带，以允许功率放大器在较高的输出功率电平下工作等。由于非线性的包络和相位失真功率放大器可以被表征为不同的输入电平和不同的频带并存储在发射机。此后，包络和相位信号可以基于存储的特征来预失真，以补偿功率放大器的非线性。

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