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21. 发明授权

US07539698B2 File name generating unit 有权
标题翻译：文件名生成单元
公开(公告)号：US07539698B2
公开(公告)日：2009-05-26
申请号：US10586497
申请日：2005-03-02
申请人： Katsuyuki Sakaniwa , Toshihiro Tanaka , Hiroshi Saitoh , Hideki Ootaka , Norikatsu Yoshida , Hisataka Ueda , Nobukatsu Okuda
发明人： Katsuyuki Sakaniwa , Toshihiro Tanaka , Hiroshi Saitoh , Hideki Ootaka , Norikatsu Yoshida , Hisataka Ueda , Nobukatsu Okuda
IPC分类号： G06F17/00
CPC分类号： G06F17/30067 , Y10S707/99943
摘要： An object of the present invention is to reduce a possibility of existence of a plurality of identical file names in files which are created by a plurality of apparatuses. This is accomplished using a file name generation apparatus having an UMID generation unit (12) generating a globally unique identifier, and a file name generation unit (14) generating a file name including the globally unique identifier generated by the UMID generation unit (12).
摘要翻译：本发明的目的是减少由多个装置创建的文件中存在多个相同文件名的可能性。这是使用具有生成全局唯一标识符的UMID生成单元（12）的文件名生成装置和生成包括由UMID生成部（12）生成的全局唯一标识符的文件名的文件名生成部（14）。

22. 发明申请

US20090061716A1 Elastic Polyurethane Yarn and Method of Manufacturing the Same 有权
标题翻译：弹性聚氨酯纱线及其制造方法
公开(公告)号：US20090061716A1
公开(公告)日：2009-03-05
申请号：US12087104
申请日：2006-12-26
申请人： Toshihiro Tanaka , Masashi Hara , Tatsuaki Kanbayashi
发明人： Toshihiro Tanaka , Masashi Hara , Tatsuaki Kanbayashi
IPC分类号： D01F6/94 , C08G18/81
CPC分类号： D01F6/70 , D01F1/07 , Y10T428/2913 , Y10T442/3976 , Y10T442/3984 , Y10T442/40
摘要： The present invention provides elastic polyurethane yarns which possess excellent elongation, recoverability, heat resistance and chemical resistance, as well as a method of manufacturing the same. The elastic polyurethane yarns comprise a polyurethane being composed mainly of a polymeric diol and a diisocyanate, and contains through incorporation a compound having within the molecule a phosphorus-nitrogen interatomic bond(s). The process can produce the elastic polyurethane yarns by adding to a solution of the polyurethane a compound having within the molecule a phosphorus-nitrogen interatomic bond(s), followed by spinning.
摘要翻译：本发明提供具有优异的伸长率，可回复性，耐热性和耐化学性的弹性聚氨酯纱线及其制造方法。弹性聚氨酯纱线包括主要由聚合二醇和二异氰酸酯组成的聚氨酯，并且通过掺入在分子内具有磷 - 氮原子间键的化合物。该方法可以通过向聚氨酯的溶液中加入在分子内具有磷 - 氮原子间键的化合物，然后纺丝来生产弹性聚氨酯纱线。

23. 发明申请

US20090052238A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20090052238A1
公开(公告)日：2009-02-26
申请号：US12258964
申请日：2008-10-27
申请人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： G11C16/00
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以优先考虑第二非易失性存储器区域，以保证存储器信息的重写操作的次数更多。

24. 发明授权

US07339827B2 Non-volatile semiconductor memory device and writing method thereof 有权
标题翻译：非挥发性半导体存储器件及其写入方法
公开(公告)号：US07339827B2
公开(公告)日：2008-03-04
申请号：US11147243
申请日：2005-06-08
申请人： Kan Yasui , Digh Hisamoto , Toshihiro Tanaka , Takashi Yamaki
发明人： Kan Yasui , Digh Hisamoto , Toshihiro Tanaka , Takashi Yamaki
IPC分类号： G11C16/06 , G11C16/32 , G11C5/06 , G11C16/08 , G11C16/24
CPC分类号： G11C16/3418 , G11C16/0466 , G11C16/3427 , H01L27/115 , H01L29/4232 , H01L29/792
摘要： In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage Vs passes a certain intermediate value Vsx, a gate voltage Vmg of the memory transistor is changed. Alternatively, there is adopted a procedure such that the gate voltage Vmg of the memory transistor is changed, and after the voltage Vmg passes a certain intermediate value Vmgx, the diffusion layer voltage Vs on the memory transistor side is changed. The values of Vsx and Vmgx are determined from the magnitude of the electric field in a gate insulating film not causing FN tunneling electron injection that causes a change in threshold voltage and the magnitude of a potential barrier against holes not causing BTBT hot hole injection.
摘要翻译：关于字线偏差的上升和下降，本发明采用使存储晶体管侧的扩散区电压Vs变化的过程，在电压Vs经过一定的中间值Vsx之后，栅极电压Vmg为存储晶体管被改变。或者，采用使存储晶体管的栅极电压Vmg改变的过程，并且在电压Vmg经过一定的中间值Vmgx之后，存储晶体管侧的扩散层电压Vs被改变。 Vsx和Vmgx的值由栅极绝缘膜中不引起FN隧穿电子注入的电场的大小确定，导致阈值电压的变化以及针对未引起BTBT热空穴注入的孔的势垒的大小。

25. 发明申请

US20070288817A1 Semiconductor integrated circuit and a method of testing the same 有权
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US20070288817A1
公开(公告)日：2007-12-13
申请号：US11785537
申请日：2007-04-18
申请人： Toshihiro Tanaka , Yutaka Shinagawa , Masahiko Kimura , Isao Nakamura
发明人： Toshihiro Tanaka , Yutaka Shinagawa , Masahiko Kimura , Isao Nakamura
IPC分类号： G01R31/28
CPC分类号： G11C29/021 , G01R31/30 , G01R31/31703 , G01R31/31725 , G01R31/3187 , G06F11/24 , G11C16/04 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2029/5004
摘要： A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.
摘要翻译：其中可以容易地与其他LSI并行设置用于确定其本身产生的脉冲的电压或宽度的控制信息的半导体集成电路（LSI），并且可以容易地校正设置信息。从外部评估装置，将预期值的电压重叠地提供给具有CPU和闪速存储器的多个LSI。每个LSI包含比较电路，其比较期望的电压值和本身产生的升压电压。 CPU参考比较结果并优化用于改变升压电压的数据寄存器中的控制数据。 CPU控制比较电路和数据寄存器，并且以自完成方式进行修整，从而以并行方式容易地对多个LSI进行修整，并且总的测试时间减少。

26. 发明授权

US07286410B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07286410B2
公开(公告)日：2007-10-23
申请号：US11195684
申请日：2005-08-03
申请人： Hiroyuki Tanikawa , Toshihiro Tanaka , Yutaka Shinagawa , Takashi Yamaki
发明人： Hiroyuki Tanikawa , Toshihiro Tanaka , Yutaka Shinagawa , Takashi Yamaki
IPC分类号： G11C16/06
CPC分类号： G11C16/344
摘要： A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area to store information in accordance with a variable threshold voltage. At least one condition of the following conditions of the first nonvolatile memory area is made different from that of the second nonvolatile memory area: erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area.
摘要翻译：半导体集成电路具有第一非易失性存储区域和第二非易失性存储区域，用于根据可变阈值电压存储信息。使第一非易失性存储区域的以下条件的至少一个条件与第二非易失性存储器区域的不同：擦除验证确定存储器栅极电压，擦除验证确定存储器电流，写入验证确定存储器栅极电压，写入验证确定存储器第一非易失性存储器区域中的电流，擦除电压，擦除电压施加时间，写入电压和写入电压施加时间。

27. 发明授权

US07190615B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07190615B2
公开(公告)日：2007-03-13
申请号：US10810672
申请日：2004-03-29
申请人： Masamichi Fujito , Yutaka Shinagawa , Kazufumi Suzukawa , Ayako Kakuda , Akira Kato , Toshihiro Tanaka
发明人： Masamichi Fujito , Yutaka Shinagawa , Kazufumi Suzukawa , Ayako Kakuda , Akira Kato , Toshihiro Tanaka
IPC分类号： G11C11/34 , G11C5/06
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/08 , G11C16/26 , G11C16/28 , G11C16/30 , G11C2207/005 , G11C2216/22
摘要： The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.
摘要翻译：能够进行电气重写的片上非易失性存储器的读取速度增加。非易失性存储器具有分层位线结构，其具有对多个存储器阵列中的每一个特定的第一位线，在多个存储器阵列之间共享的第二位线，第一选择器电路，用于为每个存储器阵列选择第一位线将所选择的第一位线连接到第二位线，以及布置在第一选择器电路的输出和第二位线之间的感测放大器。具有划分的存储器阵列的层次位线结构可以减小感测放大器的输入负载能力。

28. 发明授权

US07166220B2 Systems and methods for organic wastewater treatment 失效
标题翻译：有机废水处理系统和方法
公开(公告)号：US07166220B2
公开(公告)日：2007-01-23
申请号：US10484776
申请日：2002-11-21
申请人： Toshihiro Tanaka , Yosei Katsu , Satoshi Konishi
发明人： Toshihiro Tanaka , Yosei Katsu , Satoshi Konishi
IPC分类号： C02F3/30
CPC分类号： C02F3/121 , C02F3/1268 , C02F3/301 , Y02W10/15 , Y10S210/903
摘要： A system and method for organic wastewater treatment through denitrification and nitrification processes. The system for treating organic wastewater includes a multistage treatment tank having at least two stages in series. Each stage has a denitrification tank and a nitrification tank connected in this order. The system includes a pipe for distributing feed water to the denitrification tank in each stage, a device for filtering and separating at least a part of an activated sludge mixed liquor present in at least one nitrification tank, and a pipe for supplying at least a part of the concentrated sludge mixed liquor obtained by the filtration and separation treatment to the denitrification tank.
摘要翻译：一种通过反硝化和硝化过程进行有机废水处理的系统和方法。用于处理有机废水的系统包括具有至少两个级联的多级处理槽。每个阶段都有一个反硝化池和硝化池依次连接。该系统包括用于在每个阶段向脱氮罐分配给水的管道，用于过滤和分离存在于至少一个硝化罐中的至少一部分活性污泥混合液的装置和用于供应至少一部分的管通过过滤和分离处理获得的浓缩污泥混合液到脱氮槽中。

29. 发明申请

US20060243660A1 Method and system for the methane fermentation treatment of wastewater containing sulfur compound 有权
标题翻译：含硫化合物废水甲烷发酵处理方法及系统
公开(公告)号：US20060243660A1
公开(公告)日：2006-11-02
申请号：US10551818
申请日：2004-03-29
申请人： Kazumasa Kamachi , Yasuhiro Honma , Toshihiro Tanaka , Toshio Tsukamoto
发明人： Kazumasa Kamachi , Yasuhiro Honma , Toshihiro Tanaka , Toshio Tsukamoto
IPC分类号： C02F3/28
CPC分类号： C02F3/2846 , C02F1/722 , C02F1/76 , C02F1/78 , C02F2101/101 , C02F2303/12 , C02F2305/06 , C12M21/04 , C12M23/36 , C12M45/06 , C12M47/18 , Y02E50/343 , Y10S210/916
摘要： A method and apparatus for the anaerobic methane fermentation treatment of a wastewater containing a sulfur compound. An oxidizing agent is added to an organic wastewater to oxidize the sulfur compound contained therein to molecular sulfur before the anaerobic treatment step. The wastewater is then introduced into the anaerobic treatment step for the methane fermentation treatment thereof. The amount of the oxidizing agent to be added to the wastewater is controlled using as an indicator the concentration of the residual oxidizing agent in the water flowing into the anaerobic treatment step and/or the concentration of hydrogen sulfide in a biogas generated. The oxidizing agent may be ozone, hydrogen peroxide, sodium hypochlorite or a bromine based oxidizing agent. When the concentration of hydrogen sulfide in a biogas generated in the anaerobic treatment step is used as said indicator, the oxidizing agent may be suitably added such that the concentration of hydrogen sulfide is 3% or less.
摘要翻译：一种含有硫化合物的废水的厌氧甲烷发酵处理方法和装置。在厌氧处理步骤之前，将氧化剂加入到有机废水中以将其中所含的硫化合物氧化成分子硫。然后将废水引入用于甲烷发酵处理的厌氧处理步骤。使用作为指标控制流入厌氧处理工序的水中的残留氧化剂的浓度和/或生成的沼气中的硫化氢浓度来控制添加到废水中的氧化剂的量。氧化剂可以是臭氧，过氧化氢，次氯酸钠或溴系氧化剂。当在厌氧处理步骤中产生的沼气中的硫化氢浓度用作所述指示剂时，可以适当地加入氧化剂，使得硫化氢的浓度为3％以下。

30. 发明申请

US20060220100A1 Semicondudctor device 有权
标题翻译：半导体器件
公开(公告)号：US20060220100A1
公开(公告)日：2006-10-05
申请号：US11415129
申请日：2006-05-02
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

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