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21. 发明授权

US07333173B2 Method to simplify twin stage scanner OVL machine matching 有权
标题翻译：简化双级扫描仪OVL机器匹配的方法
公开(公告)号：US07333173B2
公开(公告)日：2008-02-19
申请号：US10818582
申请日：2004-04-06
申请人： Shun-Jiang Chiang , Chi-Hung Liao , Heng-Hsin Liu
发明人： Shun-Jiang Chiang , Chi-Hung Liao , Heng-Hsin Liu
IPC分类号： G03B27/42 , G03B27/32
CPC分类号： G03F7/70633
摘要： Multiple scanner or stepper machines are provided. A photoresist layer is coated on a monitor wafer. The photoresist layer is exposed through a mask pattern on a first of the multiple machines. The mask pattern is shifted by an offset and the photoresist layer is exposed through the mask pattern on another of the multiple machines. The shifting and exposing steps are continued for each of the multiple machines. A pattern on the monitor wafer is measured using an overlay measurement tool. Machine constants for each machine except the first machine of the multiple machines are updated based on results of the measuring to provide overlay control machine matching.
摘要翻译：提供多台扫描仪或步进机。将光致抗蚀剂层涂覆在监视器晶片上。光致抗蚀剂层通过多个机器中的第一个上的掩模图案曝光。掩模图案偏移偏移，并且光致抗蚀剂层通过多个机器中的另一个上的掩模图案曝光。对于多台机器中的每一台，继续移动和曝光步骤。使用覆盖测量工具测量监视器晶片上的图案。除了多台机器的第一台机器之外的每台机器的机器常数都会根据测量结果进行更新，以提供覆盖控制机器的匹配。

22. 发明授权

US08674355B2 Integrated circuit test units with integrated physical and electrical test regions 有权
标题翻译：集成电路测试单元，具有集成的物理和电气测试区域
公开(公告)号：US08674355B2
公开(公告)日：2014-03-18
申请号：US12980865
申请日：2010-12-29
申请人： Huan-Chi Tseng , Heng-Hsin Liu , Shu-Cheng Kuo , Chien-Chang Lee , Chun-Hung Lin
发明人： Huan-Chi Tseng , Heng-Hsin Liu , Shu-Cheng Kuo , Chien-Chang Lee , Chun-Hung Lin
IPC分类号： H01L23/58
CPC分类号： H01L23/544 , H01L22/34 , H01L23/4824 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
摘要： A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.
摘要翻译：一种装置包括在模具中的测试单元。测试单元包括物理测试区域，该物理测试区域包括有源区域和在该有源区域上并且彼此平行的多个导电线。多个导线具有基本上均匀的间隔，其中没有接触插塞直接在多个导线上并连接到多个导线。测试单元还包括电测试区域，该电测试区域包括晶体管，该晶体管具有由相同材料形成的栅极，并且处于与多个导线相同的电平; 以及连接到晶体管的源极，漏极和栅极的接触插塞。测试单元还包括邻近物理测试区域和电测试区域的对准标记。

23. 发明申请

US20120168751A1 Integrated Circuit Test Units with Integrated Physical and Electrical Test Regions 有权
标题翻译：具有综合物理和电气测试区域的集成电路测试单元
公开(公告)号：US20120168751A1
公开(公告)日：2012-07-05
申请号：US12980865
申请日：2010-12-29
申请人： Huan-Chi Tseng , Heng-Hsin Liu , Shu-Cheng Kuo , Chien-Chang Lee , Chun-Hung Lin
发明人： Huan-Chi Tseng , Heng-Hsin Liu , Shu-Cheng Kuo , Chien-Chang Lee , Chun-Hung Lin
IPC分类号： H01L23/58
CPC分类号： H01L23/544 , H01L22/34 , H01L23/4824 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
摘要： A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.
摘要翻译：一种装置包括在模具中的测试单元。测试单元包括物理测试区域，该物理测试区域包括有源区域和在该有源区域上并且彼此平行的多个导电线。多个导线具有基本上均匀的间隔，其中没有接触插塞直接在多个导线上并连接到多个导线。测试单元还包括电测试区域，该电测试区域包括晶体管，该晶体管具有由相同材料形成的栅极，并且处于与多个导线相同的电平; 以及连接到晶体管的源极，漏极和栅极的接触插塞。测试单元还包括邻近物理测试区域和电测试区域的对准标记。

24. 发明授权

US07901854B2 Wafer edge exposure unit 有权
标题翻译：晶圆边缘曝光单元
公开(公告)号：US07901854B2
公开(公告)日：2011-03-08
申请号：US12437776
申请日：2009-05-08
申请人： Po-Chang Huang , Heng-Hsin Liu , Heng-Jen Lee
发明人： Po-Chang Huang , Heng-Hsin Liu , Heng-Jen Lee
IPC分类号： G03F9/00 , G03C5/00 , G03B27/32 , G03B27/42
CPC分类号： G03B27/62 , G03F7/70425
摘要： A wafer edge exposure unit comprises a chuck for supporting a wafer. The chuck is rotatable about a central axis. A plurality of light sources are positioned or movably positionable with a common radial distance from the axis of the rotatable chuck, each light source configured to direct exposure light on a respective edge portion of the wafer simultaneously.
摘要翻译：晶片边缘曝光单元包括用于支撑晶片的卡盘。卡盘可绕中心轴线旋转。多个光源以可旋转卡盘的轴线的公共径向距离定位或可移动地定位，每个光源被配置为将曝光光同时引导到晶片的相应边缘部分。

25. 发明申请

US20100219175A1 ROTATABLE PLATE AND HEATING/COOLING ELEMENT IN PROXIMITY THERETO 有权
标题翻译：可旋转板和加热/冷却元件
公开(公告)号：US20100219175A1
公开(公告)日：2010-09-02
申请号：US12686276
申请日：2010-01-12
申请人： Jui-Chun Peng , Jacky Chung , Heng-Hsin Liu , Chun-Hung Lin
发明人： Jui-Chun Peng , Jacky Chung , Heng-Hsin Liu , Chun-Hung Lin
IPC分类号： H05B3/68
CPC分类号： H05B3/143 , H01L21/67098 , H01L21/67103 , H01L21/67115 , H01L21/67132 , H01L21/67259 , H01L21/681 , H05B1/0233 , H05B3/148 , H05B3/68
摘要： An apparatus for selectively heating/cooling one or more substrates and establishing an approximately uniform temperature in the one or more substrates during a heating or cooling event is described. In one embodiment, the apparatus comprises a rotatable hot/cold plate onto which the one or more substrates are placed and a heating/cooling element disposed in close proximity to the rotatable hot/cold plate for selectively elevating/lowering the temperature of the one or more substrates.
摘要翻译：描述了一种用于在加热或冷却事件期间选择性地加热/冷却一个或多个基底并且在一个或多个基底中建立大致均匀的温度的装置。在一个实施例中，该设备包括一个可旋转的热/冷板，一个或多个基板被放置在该可旋转的热/冷板上，以及靠近可旋转的热/冷板设置的加热/冷却元件，用于选择性地升高/降低一个或多个更多的底物。

26. 发明申请

US20050248754A1 Wafer aligner with WEE (water edge exposure) function 审中-公开
标题翻译：晶圆对准器与WEE（水边缘曝光）功能
公开(公告)号：US20050248754A1
公开(公告)日：2005-11-10
申请号：US10839625
申请日：2004-05-05
申请人： Chun-Sheng Wang , Louie Liu , Li-Kong Turn , Heng-Hsin Liu , Chi-Hung Liao , Hsin-Chun Chiang
发明人： Chun-Sheng Wang , Louie Liu , Li-Kong Turn , Heng-Hsin Liu , Chi-Hung Liao , Hsin-Chun Chiang
IPC分类号： G01B11/00 , G03F9/00
CPC分类号： G03F9/7088 , G03F9/7011
摘要： An improved photo resist coating and developing system comprising a track unit and a scanner unit is disclosed. The track unit has a coating unit for coating photo resist on a wafer. The scanner unit includes an enhanced wafer pre-alignment module, an expose stage, and a develop module. The enhanced wafer pre-alignment module is capable of performing wafer edge exposure (WEE) which conventionally required a separate WEE module as part of the track unit. By incorporating the WEE function into the wafer pre-alignment module of the scanner unit, the WEE module of the track unit is no longer required and duplication of wafer alignment and centering performed by the WEE module is eliminated.
摘要翻译：公开了一种包括轨道单元和扫描器单元的改进的光致抗蚀剂涂覆和显影系统。轨道单元具有用于在晶片上涂覆光致抗蚀剂的涂层单元。扫描器单元包括增强的晶片预对准模块，曝光台和显影模块。增强的晶片预校准模块能够执行通常需要单独的WEE模块作为轨道单元的一部分的晶片边缘曝光（WEE）。通过将WEE功能结合到扫描器单元的晶片预对准模块中，轨道单元的WEE模块不再需要，并且消除了由WEE模块执行的晶片对准和定心的复制。

27. 发明授权

US09282592B2 Rotatable heating-cooling plate and element in proximity thereto 有权
标题翻译：可旋转的加热冷却板和靠近其的元件
公开(公告)号：US09282592B2
公开(公告)日：2016-03-08
申请号：US12686276
申请日：2010-01-12
申请人： Jui-Chun Peng , Jacky Chung , Heng-Hsin Liu , Chun-Hung Lin
发明人： Jui-Chun Peng , Jacky Chung , Heng-Hsin Liu , Chun-Hung Lin
IPC分类号： H05B3/68 , H01L21/67 , H01L21/68 , H05B3/14 , H05B1/02
CPC分类号： H05B3/143 , H01L21/67098 , H01L21/67103 , H01L21/67115 , H01L21/67132 , H01L21/67259 , H01L21/681 , H05B1/0233 , H05B3/148 , H05B3/68
摘要： An apparatus for selectively heating/cooling one or more substrates and establishing an approximately uniform temperature in the one or more substrates during a heating or cooling event is described. In one embodiment, the apparatus comprises a rotatable hot/cold plate onto which the one or more substrates are placed and a heating/cooling element disposed in close proximity to the rotatable hot/cold plate for selectively elevating/lowering the temperature of the one or more substrates.
摘要翻译：描述了一种用于在加热或冷却事件期间选择性地加热/冷却一个或多个基底并且在一个或多个基底中建立大致均匀的温度的装置。在一个实施例中，该设备包括一个可旋转的热/冷板，一个或多个基板被放置在该可旋转的热/冷板上，以及靠近可旋转的热/冷板设置的加热/冷却元件，用于选择性地升高/降低一个或多个更多的底物。

28. 发明授权

US08183701B2 Structure of stacking scatterometry based overlay marks for marks footprint reduction 有权
标题翻译：基于堆叠散射法的覆盖标记的结构，用于标记尺寸减少
公开(公告)号：US08183701B2
公开(公告)日：2012-05-22
申请号：US12511638
申请日：2009-07-29
申请人： Chi-Yuan Shih , Sophia Wang , Heng-Hsin Liu , Heng-Jen Lee
发明人： Chi-Yuan Shih , Sophia Wang , Heng-Hsin Liu , Heng-Jen Lee
IPC分类号： H01L23/544 , H01L21/00
CPC分类号： G03F9/7049 , G03F7/70625 , G03F7/70633 , G03F9/7076 , G03F9/7084
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.
摘要翻译：本发明提供集成电路。集成电路包括半导体衬底; 形成在所述半导体基板上的多个材料层，每个所述材料层包括其中的电路图案; 以及形成在多个材料层中并堆叠在相同区域中的多个衍射基周期标记。基于衍射的周期标记中的一个不同于间距中基于衍射的周期性标记中的至少另一个。

29. 发明申请

US20110024924A1 METHOD AND STRUCTURE OF STACKING SCATTEROMETRY-BASED OVERLAY OR CD MARKS FOR MARK FOOTPRINT REDUCTION 有权
标题翻译：堆叠基于SCATTERMETRYET的覆盖或CD标记的标记减少的方法和结构
公开(公告)号：US20110024924A1
公开(公告)日：2011-02-03
申请号：US12511638
申请日：2009-07-29
申请人： Chi-Yuan Shih , Sophia Wang , Heng-Hsin Liu , Heng-Jen Lee
发明人： Chi-Yuan Shih , Sophia Wang , Heng-Hsin Liu , Heng-Jen Lee
IPC分类号： H01L23/544 , H01L21/66
CPC分类号： G03F9/7049 , G03F7/70625 , G03F7/70633 , G03F9/7076 , G03F9/7084
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.
摘要翻译：本发明提供集成电路。集成电路包括半导体衬底; 形成在所述半导体基板上的多个材料层，每个所述材料层包括其中的电路图案; 以及形成在多个材料层中并堆叠在相同区域中的多个衍射基周期标记。基于衍射的周期标记中的一个不同于间距中基于衍射的周期性标记中的至少另一个。

30. 发明授权

US5904570A Method for polymer removal after etching 失效
标题翻译：蚀刻后聚合物去除的方法
公开(公告)号：US5904570A
公开(公告)日：1999-05-18
申请号：US650357
申请日：1996-05-20
申请人： Sen-Fu Chen , Bao-Ru Yang , Wen-Cheng Chang , Heng-Hsin Liu
发明人： Sen-Fu Chen , Bao-Ru Yang , Wen-Cheng Chang , Heng-Hsin Liu
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/306
CPC分类号： H01L21/02071
摘要： The polymeric residues which remain after the plasma-enhanced subtractive etching of polycrystalline layers in reactive halogen-containing gases are removed by a combination ashing in oxygen gas and subsequent removal with an organic solvent.
摘要翻译：在反应性含卤素气体中的多晶层的等离子体增强的减去蚀刻之后残留的聚合物残余物通过氧气中的灰分组合并随后用有机溶剂去除而被除去。

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