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    • 24. 发明授权
    • Apparatus and method of estimating center line of intersection
    • 估计中心线交点的装置和方法
    • US07894632B2
    • 2011-02-22
    • US11858181
    • 2007-09-20
    • Jeong-Ho ParkSeong Ik ChoGee Ju Chae
    • Jeong-Ho ParkSeong Ik ChoGee Ju Chae
    • G06K9/00
    • G06K9/00798
    • Provided are a method and apparatus for estimating a center line of an intersection by recognizing a crosswalk on a road input through a camera installed in a vehicle. The apparatus includes a road information providing unit which provides information about a road being traveled based on location information of a traveling vehicle; a crosswalk recognizing unit which recognizes a crosswalk based on an input image of the intersection and the information about the road and obtains a distance from the traveling vehicle to the crosswalk; and an intersection center line estimating unit which estimates the center line of the intersection based on the information about the road and the distance from the traveling vehicle to the crosswalk. Since the center line of the intersection is estimated, the apparatus and method of estimating a center line of an intersection according to the present invention can prevent traffic accidents occurring frequently at an intersection and helps indicate direction information of ‘real vehicle navigation.’
    • 提供一种用于通过识别通过安装在车辆中的相机输入的道路上的人行横道来估计交叉路口的中心线的方法和装置。 该装置包括道路信息提供单元,其基于行驶车辆的位置信息提供关于正在行驶的道路的信息; 基于交叉口的输入图像识别人行横道的人行横道识别单元和关于道路的信息,并获得从行进车辆到人行横道的距离; 以及基于关于道路的信息和从行驶车辆到人行横道的距离来估计交叉口的中心线的交叉路口中心线估计单元。 由于估计了交点的中心线,所以根据本发明的估计交叉路口的中心线的装置和方法可以防止交叉路口频繁发生的交通事故,并且有助于指示“真正的车辆导航”的方向信息。
    • 26. 发明申请
    • MIM CAPACITOR
    • MIM电容器
    • US20080157277A1
    • 2008-07-03
    • US11964562
    • 2007-12-26
    • Jeong-Ho ParkHo-Yeong Choe
    • Jeong-Ho ParkHo-Yeong Choe
    • H01L21/283H01L29/92
    • H01L28/40
    • Embodiments relate to a metal-insulator-metal (MIM) capacitor that may include a lower insulation layer where a capacitor lower metal layer is already formed, an intermediate structure, a first conductive structure, and a second conductive structure. The intermediate structure may include a first capacitor insulation pattern, a capacitor middle metal layer, a second capacitor insulation pattern, a capacitor upper metal layer, and an insulation pattern formed in sequence over the lower insulation layer. The first conductive structure may include a copper-based material and may be coupled between the capacitor upper metal layer and the capacitor lower metal layer. The second conductive structure may include a copper-based material and is coupled to the capacitor middle metal layer.
    • 实施例涉及金属 - 绝缘体 - 金属(MIM)电容器,其可以包括已经形成电容器下部金属层的下部绝缘层,中间结构,第一导电结构和第二导电结构。 中间结构可以包括在下绝缘层上依次形成的第一电容器绝缘图案,电容器中间金属层,第二电容器绝缘图案,电容器上金属层和绝缘图案。 第一导电结构可以包括铜基材料并且可以耦合在电容器上金属层和电容器下金属层之间。 第二导电结构可以包括铜基材料并且耦合到电容器中间金属层。
    • 29. 发明申请
    • Method of manufacturing semiconductor device
    • 制造半导体器件的方法
    • US20070132036A1
    • 2007-06-14
    • US11637056
    • 2006-12-12
    • Jeong-Ho Park
    • Jeong-Ho Park
    • H01L21/336H01L29/76
    • H01L29/66553H01L29/42376H01L29/665H01L29/66545H01L29/66621H01L29/7833
    • A method for manufacturing a semiconductor device, includes sequentially forming a first insulation film and a dummy gate electrode on a semiconductor substrate; forming a lightly doped junction region by using the dummy gate electrode as a mask, forming a first spacer on a side wall of the dummy gate electrode, and then forming a heavily doped junction region. The method further includes forming a second insulation film on the semiconductor substrate where the heavily doped junction region is formed, and removing the dummy gate electrode to form a cavity exposing a portion of the first insulation layer; forming a second spacer on a side wall of the cavity; sequentially forming a gate insulation film and a gate conductor on the second spacer, and then removing the second insulation film and a portion of the gate insulation film; and forming a salicide film on a top of the gate conductor and in the lightly doped junction region.
    • 一种半导体器件的制造方法,包括在半导体衬底上依次形成第一绝缘膜和伪栅电极; 通过使用伪栅极电极作为掩模形成轻掺杂的结区域,在虚拟栅电极的侧壁上形成第一间隔物,然后形成重掺杂的结区域。 该方法还包括在半导体衬底上形成第二绝缘膜,其中形成重掺杂结区,以及去除伪栅电极以形成露出第一绝缘层的一部分的空腔; 在所述空腔的侧壁上形成第二间隔件; 在所述第二间隔物上依次形成栅极绝缘膜和栅极导体,然后去除所述第二绝缘膜和所述栅极绝缘膜的一部分; 以及在栅极导体的顶部和在轻掺杂的结区中形成自对准硅膜。