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    • 21. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US5455796A
    • 1995-10-03
    • US105203
    • 1993-08-10
    • Takashi InuiKiyotaka OkuzawaYoshihiro Ogata
    • Takashi InuiKiyotaka OkuzawaYoshihiro Ogata
    • G11C11/401G11C11/407G11C29/12G11C29/34H01L27/10G11C11/40
    • G11C29/34
    • A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory/device can be shortened, and the power consumption can be cut.In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.
    • 一种半导体存储器件,其特征在于可以缩短半导体存储器/器件的干扰测试时间,并且可以削减功耗。 在本发明的半导体存储器件的干扰测试中,以对应于元件隔离布局的规定间隔同时选择多个字线。 当对应于元件隔离布局选择字线时,可以排除由元件隔离状态引起的干扰。 由于同时选择多个字线,所以可以缩短操作时间。 由于在读出放大器未复位的同时,字线保持在选择状态,所以尽管同时选择了多个字线,功耗也没有增加。
    • 22. 发明申请
    • Self-emission unit and method of manufacturing the same
    • 自发射单元及其制造方法
    • US20070063648A1
    • 2007-03-22
    • US11520016
    • 2006-09-13
    • Yoshihiro Ogata
    • Yoshihiro Ogata
    • H01J1/62
    • H04M1/0266H01L51/5237H01L51/524
    • It is an object of the present invention to provide an improved method of manufacturing a self-emission unit including a self-emission module having self-emission elements formed on a substrate, and a frame for protecting the self-emission modules, without carrying out some troublesome steps, thus making it possible to manufacture the self-emission unit in a shortened time. Another object of the present invention is to provide an improved self-emission unit capable of being attached to an attachment base with a high precision. The self-emission unit has a self-emission module and a frame. The frame is provided to cover a part or the whole of the self-emission module so as to protect the same. Further, the frame has fastening sections for attaching the self-emission module to an attachment base. The frame is formed integrally with the self-emission module so that it is possible to avoid some troublesome steps and thus shorten manufacturing time. The foregoing structure also makes it possible to improve an attachment precision when attaching the self-emission unit to an attachment base.
    • 本发明的目的是提供一种制造自发射单元的改进方法,该自发射单元包括在基板上形成自发射元件的自发射模块,以及用于保护自发射模块的框架,而不进行 一些麻烦的步骤,从而可以在缩短的时间内制造自发射单元。 本发明的另一个目的是提供一种能够以高精度附着到安装底座上的改进的自发射单元。 自发射单元具有自发射模块和框架。 该框架被设置为覆盖自发射模块的一部分或全部以便保护该自发射模块。 此外,框架具有用于将自发射模块附接到附接基座的紧固部分。 框架与自发射模块一体地形成,从而可以避免一些麻烦的步骤,从而缩短制造时间。 上述结构还使得可以在将自发射单元附接到安装基座时提高安装精度。
    • 23. 发明授权
    • Semiconductor device array having dense memory cell array and hierarchical bit line scheme
    • 具有密集存储单元阵列和分层位线方案的半导体器件阵列
    • US06768663B2
    • 2004-07-27
    • US10428436
    • 2003-05-02
    • Yoshihiro Ogata
    • Yoshihiro Ogata
    • G11C506
    • G11C7/18H01L27/10882H01L27/10897
    • A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208t) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208t) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another. In a switch configuration, the reconnector circuits (210a and 210b) couple a matching lower conductive segment (204a-204h) to each higher conductive segment of the adjacent higher conductive segment pairs.
    • 公开了一种半导体器件结构(200)。 排列成行和列的单元电路(202)耦合到下导电段(204a-204h)。 下导电段(204a-204h)被布置成“打开”构造,允许相邻的单元电路(202)被同时访问。 下导电段(204a-204h)通过重新检测电路(210a和210b)耦合到较高导电段(208a-208t)。 较高导电段(208a-208t)被布置在差分型放大器(212a和212b)之间的折叠对(208a / 208d,208b / 208e和208c / 208f)中。 检测器电路(210a和210b)各自具有重新连接配置和开关配置。 在重新连接配置中,重新连接电路(210a和210b)将相邻折叠的较高导电段对彼此耦合。 在开关配置中,再检测器电路(210a和210b)将匹配的下导电段(204a-204h)耦合到相邻较高导电段对的每个较高导电段。