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21. 发明授权

US06578169B1 Data failure memory compaction for semiconductor test system 失效
标题翻译：半导体测试系统的数据故障记忆压缩
公开(公告)号：US06578169B1
公开(公告)日：2003-06-10
申请号：US09545730
申请日：2000-04-08
申请人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
发明人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
IPC分类号： G01R3128
CPC分类号： G01R31/31935 , G11C29/56
摘要： A semiconductor test system for testing a semiconductor device under test (DUT) is able to store failure data in a data failure memory with small memory capacity. The semiconductor test system includes a pattern memory for storing pattern data therein to produce a test pattern to be supplied to the DUT, means for evaluating an output signal of the DUT and producing failure data when there is a fail therein, a data failure memory for storing the failure data, and compaction means for assigning a plurality of addresses of the pattern memory to a single address of the data failure memory in a first test operation so that failure data occurred for each group of addresses of the pattern memory is stored in a corresponding address of the data failure memory, and for executing a second test operation for only a group of addresses of the pattern memory in which the failure data is detected without an address compaction.
摘要翻译：用于测试被测半导体器件（DUT）的半导体测试系统能够将故障数据存储在具有小存储器容量的数据故障存储器中。半导体测试系统包括用于在其中存储模式数据以产生要提供给DUT的测试模式的模式存储器，用于评估DUT的输出信号的装置和当其中存在故障时产生故障数据的装置，用于存储故障数据，以及压缩装置，用于在第一测试操作中将模式存储器的多个地址分配给数据故障存储器的单个地址，使得针对模式存储器的每组地址发生的故障数据被存储在数据故障存储器的对应地址，以及仅针对其中检测到故障数据而不进行地址压缩的模式存储器的一组地址执行第二测试操作。

22. 发明授权

US06532561B1 Event based semiconductor test system 失效
标题翻译：基于事件的半导体测试系统
公开(公告)号：US06532561B1
公开(公告)日：2003-03-11
申请号：US09406300
申请日：1999-09-25
申请人： James Alan Turnquist , Shigeru Sugamori , Rochit Rajsuman , Hiroaki Yamoto
发明人： James Alan Turnquist , Shigeru Sugamori , Rochit Rajsuman , Hiroaki Yamoto
IPC分类号： G01R3128
CPC分类号： G01R31/31922 , G01R31/31921
摘要： An event based test system is configured to test an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The event based test system includes an event memory for storing timing data of each event formed with an integer multiple of a reference clock period and a fraction of the reference clock period wherein the timing data represents a time difference between a current event and a reference point, an address sequencer for generating address data for accessing the event memory, a timing count and scaling logic for generating an event start signal, an event generation unit for generating each event based on the event start signal and data indicating the fraction of the reference clock period, and a host computer for controlling an overall operation of the event based test system.
摘要翻译：基于事件的测试系统被配置为通过向DUT提供测试信号并在选通信号的定时评估DUT的输出来测试被测电子设备（DUT）。基于事件的测试系统包括事件存储器，用于存储以参考时钟周期的整数倍和参考时钟周期的一部分形成的每个事件的定时数据，其中定时数据表示当前事件与参考点之间的时间差，用于产生访问事件存储器的地址数据的地址序列器，用于产生事件开始信号的定时计数和缩放逻辑，用于基于事件开始信号产生每个事件的事件生成单元和指示参考时钟的分数的数据以及用于控制基于事件的测试系统的整体操作的主计算机。

23. 发明授权

US06445208B1 Power source current measurement unit for semiconductor test system 失效
标题翻译：半导体测试系统的电源电流测量单元
公开(公告)号：US06445208B1
公开(公告)日：2002-09-03
申请号：US09544058
申请日：2000-04-06
申请人： Shigeru Sugamori
发明人： Shigeru Sugamori
IPC分类号： G01R3136
CPC分类号： G01R31/31921 , G01R31/3004 , G01R31/3191
摘要： A semiconductor test system having a power source current measurement unit for measuring a power source current of a device under test with high speed and accuracy. The power source measurement unit includes a DA converter for generating a source voltage, an operational amplifier for forming a negative feedback loop and supplying the source voltage to a power pin of the device under test thereby supplying a power source current to the power pin, a voltage amplifier for amplifying a voltage representing the amount of power source current supplied to the device under test, an integration circuit for integrating an output signal of the voltage amplifier for a predetermined integration time, and an AD converter for converting an output signal of the integration circuit to a digital signal after the integration time.
摘要翻译：一种具有电源电流测量单元的半导体测试系统，用于以高速度和精确度测量被测器件的电源电流。电源测量单元包括用于产生源电压的DA转换器，用于形成负反馈回路的运算放大器，并将源电压提供给被测器件的电源引脚，从而向电源引脚提供电源电流; 电压放大器，用于放大表示提供给被测器件的电源电流量的电压，用于对预定积分时间积分电压放大器的输出信号的积分电路和用于转换积分时间的输出信号的AD转换器电路到数字信号后的积分时间。

24. 发明授权

US06377065B1 Glitch detection for semiconductor test system 失效
标题翻译：半导体测试系统的毛刺检测
公开(公告)号：US06377065B1
公开(公告)日：2002-04-23
申请号：US09548875
申请日：2000-04-13
申请人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
发明人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
IPC分类号： G01R3126
CPC分类号： G01R31/31937 , G01R31/31922
摘要： A semiconductor test system has a glitch detection function for detecting glitches in an output signal from a device under test to accurately evaluate the device under test (DUT) . The semiconductor test system includes an event memory for storing event data, an event generator for producing test patterns, strobe signals and expected patterns based on the event data from the event memory, a pin electronics for transmitting the test pattern from the event generator to the DUT and receiving an output signal of the DUT and sampling the output signal by timings of the strobe signals, a pattern comparator for comparing sampled output data with the expected patterns, and a glitch detection unit for receiving the output signal from the DUT and detecting a glitch in the output signal by counting a number of edges in the output signal and comparing an expected number of edges.
摘要翻译：半导体测试系统具有毛刺检测功能，用于检测来自被测器件的输出信号中的毛刺，以准确地评估待测器件（DUT）。半导体测试系统包括用于存储事件数据的事件存储器，用于产生测试图案的事件发生器，用于产生来自事件存储器的事件数据的选通信号和预期模式，用于将测试模式从事件发生器发送到 DUT并接收DUT的输出信号，并通过选通信号的定时对输出信号进行采样，用于将采样输出数据与预期模式进行比较的模式比较器，以及用于从DUT接收输出信号的检测单元通过对输出信号中的边缘数进行计数并比较预期的边缘数量来在输出信号中产生毛刺。

25. 发明授权

US4414665A Semiconductor memory device test apparatus 失效
标题翻译：半导体存储器件测试装置
公开(公告)号：US4414665A
公开(公告)日：1983-11-08
申请号：US206902
申请日：1980-11-14
申请人： Kenji Kimura , Shigeru Sugamori , Kohji Ishikawa , Naoaki Narumi
发明人： Kenji Kimura , Shigeru Sugamori , Kohji Ishikawa , Naoaki Narumi
IPC分类号： G11C29/56 , G06F11/26
CPC分类号： G11C29/56
摘要： A memory device under test is accessed by an address generated by a pattern generator to write therein data and to read the data out to be compared with expected data, and the comparison result is stored in the fault-address memory by the same address after reading out therefrom the content of the address. When a disagreement is detected through the comparison, it is counted; however, the count operation is inhibited if the data read out from the fault-address memory is a fault data. When the counted number exceeds a predetermined value, a fault signal is generated. After the test is terminated, an address counter is operated, the fault-address memory is read out by the content of the address counter, and when fault data is detected from the output read out, the content of the address counter is fetched into the CPU.
摘要翻译：受测试的存储器件由模式发生器产生的地址访问，以便在其中写入数据并读出要与预期数据进行比较的数据，并且比较结果在读取之后被相同的地址存储在故障地址存储器中从中输出地址的内容。当通过比较检测到不一致时，它是计数的; 然而，如果从故障寻址存储器读出的数据是故障数据，则计数操作被禁止。当计数值超过预定值时，产生故障信号。测试结束后，操作地址计数器，通过地址计数器的内容读取故障地址存储器，当从输出读出检测到故障数据时，将地址计数器的内容取入中央处理器。

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