专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US09230744B2 MEMS device and method of manufacturing the same 有权
标题翻译： MEMS器件及其制造方法
公开(公告)号：US09230744B2
公开(公告)日：2016-01-05
申请号：US13621982
申请日：2012-09-18
申请人： Kei Watanabe , Yoshiaki Shimooka , Tomohiro Saito , Tamio Ikehashi
发明人： Kei Watanabe , Yoshiaki Shimooka , Tomohiro Saito , Tamio Ikehashi
IPC分类号： H01G5/00 , H01G5/16 , H01G5/011
CPC分类号： H01G5/16 , H01G5/011 , Y10T29/42
摘要： According to one embodiment, a MEMS element comprises a first electrode fixed on a substrate, a second electrode formed above the first electrode to face it, and vertically movable, a first anchor portion formed on the substrate and configured to support the second electrode, and a first spring portion configured to connect the second electrode and the first anchor portion. The first spring portion includes a liner layer includes a brittle material in contact with the second electrode and the first anchor portion, and a base layer formed on the liner layer, includes a brittle material having a composition different from that of the liner layer, and having a film thickness larger than that of the liner layer.
摘要翻译：根据一个实施例，MEMS元件包括固定在基板上的第一电极，形成在第一电极上面以面对它并且可垂直移动的第二电极，形成在基板上并构造成支撑第二电极的第一锚定部分，以及构造成连接第二电极和第一锚定部分的第一弹簧部分。第一弹簧部分包括：衬垫层，包括与第二电极和第一锚定部分接触的脆性材料，以及形成在衬垫层上的基底层，包括具有不同于衬垫层的组成的脆性材料，以及其膜厚度大于衬层的膜厚。

22. 发明授权

US08987829B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08987829B2
公开(公告)日：2015-03-24
申请号：US12100621
申请日：2008-04-10
申请人： Yoshiaki Shimooka , Takashi Izumida , Hiroki Okamoto
发明人： Yoshiaki Shimooka , Takashi Izumida , Hiroki Okamoto
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823807 , H01L27/092 , H01L29/7843 , H01L29/7846
摘要： A semiconductor device may include a p-channel semiconductor active region and an n-channel semiconductor active region. An element isolation insulating layer electrically isolates the p-channel semiconductor active region from the n-channel semiconductor active region. An insulating layer made of a different material, being in contact with both ends, in its channel length direction, of the p-channel semiconductor active region applies a compression stress in the channel length direction to a channel of the p-channel semiconductor active region. The p-channel semiconductor active region is surrounded by the insulating layer, in the channel length direction, of the p-channel semiconductor active region and by the element isolation insulating layer, parallel to the channel length direction, of the p-channel semiconductor active region. The n-channel semiconductor active region is surrounded by the element isolation insulating layer.
摘要翻译：半导体器件可以包括p沟道半导体有源区和n沟道半导体有源区。元件隔离绝缘层将p沟道半导体有源区与n沟道半导体有源区电隔离。由p沟道半导体有源区的沿其沟道长度方向与两端接触的不同材料制成的绝缘层将沟道长度方向的压缩应力施加到p沟道半导体有源区的沟道。 p沟道半导体有源区被p沟道半导体有源区的沟道长度方向的绝缘层和与沟道长度方向平行的元件隔离绝缘层包围，地区。 n沟道半导体有源区被元件隔离绝缘层包围。

23. 发明授权

US08921951B2 MEMS device and manufacturing method thereof 有权
标题翻译： MEMS器件及其制造方法
公开(公告)号：US08921951B2
公开(公告)日：2014-12-30
申请号：US12715573
申请日：2010-03-02
申请人： Yoshiaki Shimooka
发明人： Yoshiaki Shimooka
IPC分类号： H01L29/84 , B81B3/00 , H03H3/007 , H03H9/10 , H03H9/02
CPC分类号： B81B3/0051 , B81B2201/0271 , B81C2203/0136 , H03H3/0072 , H03H9/02259 , H03H9/1057 , H03H2009/0244
摘要： A MEMS device includes: a movable element supported by a supporting member on a substrate; an encapsulation structure provided above the substrate so as to encapsulate the movable element; and a fin that is made of an insulation film, provided above the substrate, and provided inside of the encapsulation structure and outside of the movable element, and a part of the fin being positioned between a height from the substrate when the movable element are turned ON and a height from the substrate when the movable element are turned OFF.
摘要翻译： MEMS器件包括：由衬底上的支撑构件支撑的可移动元件; 封装结构，设置在所述衬底上方以封装所述可移动元件; 以及设置在所述基板上方并且设置在所述封装结构体内部和所述可动元件的外侧的绝缘膜的翅片，并且所述翅片的一部分位于与所述基板的高度之间，当所述可动元件转动时 ON，并且当可移动元件关闭时与基板的高度。

24. 发明申请

US20130249064A1 STACKED PACKAGE AND METHOD OF MANUFACTURING STACKED PACKAGE 审中-公开
标题翻译：堆叠封装和制造堆叠封装的方法
公开(公告)号：US20130249064A1
公开(公告)日：2013-09-26
申请号：US13613434
申请日：2012-09-13
申请人： Hiroaki YAMAZAKI , Yoshiaki Sugizaki , Kazuyuki Higashi , Yoshiaki Shimooka
发明人： Hiroaki YAMAZAKI , Yoshiaki Sugizaki , Kazuyuki Higashi , Yoshiaki Shimooka
IPC分类号： H01L23/48 , H01L21/50 , H01L23/552
CPC分类号： H01L23/48 , B81B2207/012 , B81C1/00238 , B81C2203/0792 , H01L21/50 , H01L21/561 , H01L23/3114 , H01L23/552 , H01L24/05 , H01L24/13 , H01L2224/02381 , H01L2224/0401 , H01L2224/05548 , H01L2224/05559 , H01L2224/05572 , H01L2224/13021 , H01L2224/13022 , H01L2224/13024 , H01L2924/00014 , H01L2924/1461 , H01L2924/00 , H01L2224/05552
摘要： According to an embodiment, there are provided a semiconductor chip having a semiconductor element formed thereon, a pad electrode formed on the semiconductor chip and connected to the semiconductor element, a resin layer formed on the semiconductor chip, a foundation insulating layer on which an electronic element and an internal electrode are formed, a hollow body formed on the foundation insulating layer to cover the electronic element and having a top surface side embedded in the resin layer, an opening portion formed on the foundation insulating layer and configured to expose a back surface of the internal electrode, and a conductive layer configured to connect the pad electrode and the internal electrode through the opening portion.
摘要翻译：根据实施例，提供了一种其上形成有半导体元件的半导体芯片，形成在半导体芯片上并连接到半导体元件的焊盘电极，形成在半导体芯片上的树脂层，基础绝缘层，电子形成内部电极，形成在所述基础绝缘层上以覆盖所述电子元件并且具有嵌入在所述树脂层中的顶面侧的中空体，形成在所述基础绝缘层上并且被配置为暴露所述背面的开口部以及被配置为通过所述开口部连接所述焊盘电极和所述内部电极的导电层。

25. 发明申请

US20120049390A1 ELECTRICAL COMPONENT AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：电气部件及其制造方法
公开(公告)号：US20120049390A1
公开(公告)日：2012-03-01
申请号：US13215457
申请日：2011-08-23
申请人： Yoshiaki Shimooka , Yoshiaki Sugizaki
发明人： Yoshiaki Shimooka , Yoshiaki Sugizaki
IPC分类号： H01L23/28 , H01L21/56
CPC分类号： B81C1/00333 , B81C2203/0136 , B81C2203/0145 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, an electrical component comprises a substrate, an element, a first layer, and a second layer. The element is formed on the substrate. The first layer forms a cavity accommodating the element on the substrate and includes through holes. The second layer is formed on the first layer and seals the through holes. The first layer includes the first film formed on the lower side and the second film which is formed on the first film and has a lower coefficient of thermal expansion than the first film.
摘要翻译：根据一个实施例，电气部件包括衬底，元件，第一层和第二层。元件形成在基板上。第一层形成容纳元件的空腔，并且包括通孔。第二层形成在第一层上并密封通孔。第一层包括在下侧形成的第一膜和形成在第一膜上的第二膜，并且具有比第一膜更低的热膨胀系数。

26. 发明申请

US20110291167A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110291167A1
公开(公告)日：2011-12-01
申请号：US13048048
申请日：2011-03-15
申请人： Yoshiaki Shimooka , Hiroaki Yamazaki
发明人： Yoshiaki Shimooka , Hiroaki Yamazaki
IPC分类号： H01L29/78
CPC分类号： B81C1/00246 , B81B2201/0221 , B81C2203/0735 , B81C2203/0771 , H01G5/40 , H01L2224/13 , H01L2924/1461 , H01L2924/00
摘要： In one embodiment, a semiconductor device includes a substrate having a through hole, and a MEMS capacitor provided above the substrate. The device further includes an integrated circuit configured to control the MEMS capacitor, the circuit including transistors on the substrate and being provided under the MEMS capacitor and on the substrate. Further, an area on the substrate immediately under the MEMS capacitor overlaps at least partially with the through hole.
摘要翻译：在一个实施例中，半导体器件包括具有通孔的衬底和设置在衬底上方的MEMS电容器。该装置还包括被配置为控制MEMS电容器的集成电路，该电路包括在该基板上的晶体管并且设置在该MEMS电容器下方和该基板上。此外，在MEMS电容器正下方的衬底上的区域至少部分地与通孔重叠。

27. 发明申请

US20110095382A1 MEMS DEVICE 审中-公开
标题翻译： MEMS器件
公开(公告)号：US20110095382A1
公开(公告)日：2011-04-28
申请号：US12907110
申请日：2010-10-19
申请人： Yoshiaki Shimooka
发明人： Yoshiaki Shimooka
IPC分类号： H01L29/84 , H01L21/02
CPC分类号： B81C1/00476 , B81B2207/097 , B81C2203/0136 , B81C2203/0145
摘要： A MEMS device of an embodiment includes: a MEMS element; a first cavity region provided on the MEMS element; a second cavity region provided on a surrounding portion outside the MEMS element, the second cavity region having a lower height than the first cavity region; a third cavity region provided on a surrounding portion outside the second cavity region, the third cavity region having a lower height than the second cavity region; an insulating film provided to cover upper portions and side surfaces of the first to the third cavity regions; an opening provided in the insulating film on the first to the third cavity regions; and a sealant provided on the insulating film to seal the opening and to retain the first to the third cavity regions.
摘要翻译：实施例的MEMS器件包括：MEMS元件; 设置在所述MEMS元件上的第一腔区; 第二空腔区域，设置在MEMS元件外部的周围部分上，第二空腔区域具有比第一空腔区域低的高度; 第三腔区，设置在第二腔区外的周围部分，第三腔区具有比第二腔区更低的高度; 绝缘膜，设置为覆盖第一至第三腔区的上表面和侧表面; 设置在第一至第三腔区域的绝缘膜上的开口; 以及设置在绝缘膜上以密封开口并保持第一至第三腔区的密封剂。

28. 发明授权

US07574090B2 Semiconductor device using buried oxide layer as optical wave guides 有权
标题翻译：半导体器件采用埋氧层作为光波导
公开(公告)号：US07574090B2
公开(公告)日：2009-08-11
申请号：US11432483
申请日：2006-05-12
申请人： Yoshiaki Shimooka
发明人： Yoshiaki Shimooka
IPC分类号： G02B6/10
CPC分类号： G02B6/4214
摘要： A semiconductor optical wave guide device is described in which a buried oxide layer (BOX) is capable of guiding light. Optical signals may be transmitted from one part of the semiconductor device to another, or with a point external to the semiconductor device, via the wave guide. In one example, an optical wave guide is provided including a core insulating layer encompassed by a clad insulating layer. The semiconductor device may contain an etched hole for guiding light to and from the core insulating layer from a transmitter or to a receiver.
摘要翻译：描述了一种半导体光波导装置，其中掩埋氧化物层（BOX）能够引导光。光信号可以经由波导从半导体器件的一部分传输到另一半导体器件或半导体器件外部。在一个示例中，提供了包括由包层绝缘层包围的芯绝缘层的光波导。半导体器件可以包含蚀刻孔，用于将光从发射器或接收器引导到芯绝缘层和从芯绝缘层引导光。

29. 发明申请

US20070197024A1 Interconnect structure and method for semiconductor device 有权
标题翻译：半导体器件的互连结构和方法
公开(公告)号：US20070197024A1
公开(公告)日：2007-08-23
申请号：US11356146
申请日：2006-02-17
申请人： Yoshiaki Shimooka , Tadashi Iijima
发明人： Yoshiaki Shimooka , Tadashi Iijima
IPC分类号： H01L21/4763
CPC分类号： H01L21/76801 , H01L21/7688
摘要： An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the dielectric, but may be removed from the high density areas to allow the lower density areas to increase outgassing. The lower density areas may then compensate for increased outgassing on the high density areas due to the trench features, and may result in an overall device with a more stable dielectric constant across the device.
摘要翻译：半导体器件中的互连方法可以包括检查层间电介质的各个区域以识别具有高密度或沟槽特征的浓度的区域的步骤。可以将绝缘体层添加到电介质中以有助于从电介质中除去吸收的杂质，但是可以从高密度区域移除，以允许较低密度区域增加除气。然后，由于沟槽特征，较低密度区域可以补偿在高密度区域上的增加的放气，并且可能导致整个器件在整个器件上具有更稳定的介电常数。

30. 发明授权

US08867875B2 Semiconductor device using buried oxide layer as optical wave guides 有权
标题翻译：半导体器件采用埋氧层作为光波导
公开(公告)号：US08867875B2
公开(公告)日：2014-10-21
申请号：US12496007
申请日：2009-07-01
申请人： Yoshiaki Shimooka
发明人： Yoshiaki Shimooka
IPC分类号： G02B6/34 , G02B6/42 , H01L21/00 , H01L21/84
CPC分类号： G02B6/4214
摘要： A semiconductor optical wave guide device is described in which a buried oxide layer (BOX) is capable of guiding light. Optical signals may be transmitted from one part of the semiconductor device to another, or with a point external to the semiconductor device, via the wave guide. In one example, an optical wave guide is provided including a core insulating layer encompassed by a clad insulating layer. The semiconductor device may contain an etched hole for guiding light to and from the core insulating layer from a transmitter or to a receiver.
摘要翻译：描述了一种半导体光波导装置，其中掩埋氧化物层（BOX）能够引导光。光信号可以经由波导从半导体器件的一部分传输到另一半导体器件或半导体器件外部。在一个示例中，提供了包括由包层绝缘层包围的芯绝缘层的光波导。半导体器件可以包含蚀刻孔，用于将光从发射器或接收器引导到芯绝缘层和从芯绝缘层引导光。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式