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21. 发明授权

US5568436A Semiconductor device and method of screening the same 失效
公开(公告)号：US5568436A
公开(公告)日：1996-10-22
申请号：US480926
申请日：1995-06-07
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C11/408 , G11C11/409 , G11C29/00 , G11C29/06 , G11C29/46 , G11C29/50 , G11C7/00 , G11C8/00
CPC分类号： G11C11/4085 , G11C29/46 , G11C29/50 , G11C5/145 , G11C5/147 , G11C11/401
摘要： A semiconductor device comprising a plurality of circuit blocks to which various potentials, including at least one potential either raised or lowered, are assigned. The device further comprises means for selectively and reversely changing the potentials assigned to the circuit blocks.

22. 发明授权

US5553024A Semiconductor memory utilizing RAS and CAS signals to control the latching of first and second read or write data 失效
标题翻译：半导体存储器利用RAS和CAS信号来控制第一和第二读或写数据的锁存
公开(公告)号：US5553024A
公开(公告)日：1996-09-03
申请号：US419769
申请日：1995-04-10
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1051 , G11C11/4096 , G11C7/1078 , G11C7/1093
摘要： An improved semiconductor memory device such as a dynamic random access memory (DRAM) includes a latch circuit and an output buffer. The latch circuit latches first data read out from one memory cell of a memory cell array during one cycle of a row address strobe (RAS) signal and during one cycle of a column address strobe (CAS) signal. During another cycle of the row address strobe signal and during another cycle of the column address strobe signal, the first data is transferred from the latch circuit to the output buffer and the latch circuit latches second data read out from another memory cell of the memory cell array. The use of the latch circuit and output buffer reduces access time and increases the data transfer rate of the memory device.
摘要翻译：诸如动态随机存取存储器（DRAM）的改进的半导体存储器件包括锁存电路和输出缓冲器。在行地址选通（RAS）信号的一个周期和列地址选通（CAS）信号的一个周期期间，锁存电路锁存从存储单元阵列的一个存储单元读出的第一数据。在行地址选通信号的另一周期期间，并且在列地址选通信号的另一个周期期间，第一数据从锁存电路传送到输出缓冲器，并且锁存电路锁存从存储单元的另一存储单元读出的第二数据数组。使用锁存电路和输出缓冲器减少存取时间并增加存储器件的数据传输速率。

23. 发明授权

US5500815A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5500815A
公开(公告)日：1996-03-19
申请号：US981541
申请日：1992-11-25
申请人： Satoru Takase , Tohru Furuyama
发明人： Satoru Takase , Tohru Furuyama
IPC分类号： G11C11/401 , G11C11/404 , G11C11/405 , G11C11/56 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C11/24 , G11C11/40
CPC分类号： G11C11/565 , G11C11/404 , H01L27/10805
摘要： A semiconductor memory cell comprises a first cascade gate, formed on a semiconductor substrate, having its end connected to a first node, and a plurality of MOS transistors which are connected in cascade, a plurality of data storage capacitors, formed on the semiconductor substrate, each of which has its end connected to that end of a corresponding one of the MOS transistors which is opposite to the first node, and a device isolation MOS transistor formed between the memory cell and another semiconductor memory cell which are arranged side by side on the semiconductor substrate.
摘要翻译：半导体存储单元包括形成在半导体衬底上的第一级联栅极，其端部连接到第一节点，以及串联连接的多个MOS晶体管，形成在半导体衬底上的多个数据存储电容器，其每个端部连接到与第一节点相对的相应的一个MOS晶体管的端部，以及形成在存储单元和另一半导体存储单元之间的器件隔离MOS晶体管，它们并排布置在半导体衬底。

24. 发明授权

US5410505A Semiconductor memory device having a memory cell unit including a plurality of transistors connected in series 失效
标题翻译：具有包括串联连接的多个晶体管的存储单元的半导体存储器件
公开(公告)号：US5410505A
公开(公告)日：1995-04-25
申请号：US201090
申请日：1994-02-24
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： H01L27/108 , G11C11/405 , G11C11/56 , H01L21/8242 , G11C7/02
CPC分类号： G11C11/565
摘要： A semiconductor memory device comprising a memory cell array having a plurality of dynamic memory cells, each of the memory cells including a plurality of MOS transistors connected by cascade connection, capacitors for storing data each having an end connected to an end of a corresponding one of the MOS transistors, and a register arranged in a column portion of the memory cell array, for temporarily registering the data read from the memory cells in a time series manner.
摘要翻译：一种半导体存储器件，包括具有多个动态存储单元的存储单元阵列，每个存储单元包括通过级联连接的多个MOS晶体管，用于存储数据的电容器，每个存储单元的端部连接到相应的一个 MOS晶体管和布置在存储单元阵列的列部分中的寄存器，用于以时间序列方式临时登记从存储器单元读取的数据。

25. 发明授权

US5383160A Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US5383160A
公开(公告)日：1995-01-17
申请号：US187517
申请日：1994-01-28
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： G11C11/401 , G11C7/10 , G11C11/404 , G11C11/405 , G11C11/407 , G11C11/56 , G11C13/00
CPC分类号： G11C11/404 , G11C11/565 , G11C7/1006
摘要： A DRAM includes a memory cell array having cascade-connected type memory cells arranged in a matrix form and each capable of storing plural-bit information in the unit of bit, sense amplifiers each arranged for a preset number of columns in the memory cell array and disposed in the central portion of the bit lines of the preset number of columns in the arrangement direction, switching circuits disposed on both sides of each of the sense amplifiers, for electrically and selectively connecting the preset number of columns to the sense amplifier, an address designation circuit for separately and serially designating addresses of a plurality of memory cells disposed on both sides of the sense amplifier in the same column of the memory cell array, a word line driving circuit for selectively driving a word line connected to a memory cell of an address designated by the address designation circuit, a column selection circuit for effecting the column selection of the memory cell array, and an access control circuit for time-serially reading out plural-bit information from one of the memory cells storing storage information and lying on one side of the sense amplifier and sequentially rewriting the plural-bit information into one of the memory cells lying on the other side of the sense amplifier and set in a non-use state at the time of serial access to a plurality of memory cells in a desired column of the memory cell array.
摘要翻译： DRAM包括具有以矩阵形式布置的级联连接型存储单元的存储单元阵列，并且每个存储单元阵列能够以位为单位存储多位信息，每个排列在存储单元阵列中的预设数量的列的读出放大器，设置在布置方向上的预设列数的位线的中心部分中，设置在每个读出放大器两侧的开关电路，用于电和选择性地将预设数量的列连接到读出放大器，地址指定电路，用于单独和串行地指定设置在存储单元阵列的同一列中的读出放大器两侧的多个存储单元的地址;字线驱动电路，用于选择性地驱动连接到存储单元阵列的存储单元的字线由地址指定电路指定的地址，用于进行存储单元阵列的列选择的列选择电路，以及访问控制电路，用于从存储存储信息的一个存储单元中逐时读出多位信息，并且位于读出放大器的一侧，并且将多位信息依次重写为位于另一侧的存储单元之一并且在串行访问存储器单元阵列的期望列中的多个存储器单元时将其设置为非使用状态。

26. 发明授权

US5377152A Semiconductor memory and screening test method thereof 失效
标题翻译：半导体存储器及其筛选试验方法
公开(公告)号：US5377152A
公开(公告)日：1994-12-27
申请号：US978883
申请日：1992-11-19
申请人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
发明人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
IPC分类号： G11C29/02 , G11C29/24 , G11C29/50 , G11C7/00
CPC分类号： G11C29/025 , G11C29/02 , G11C29/028 , G11C29/24 , G11C29/50 , G11C11/401 , G11C2029/5004 , G11C2029/5006
摘要： A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.
摘要翻译：半导体存储器包括动态型存储单元阵列，其布置成形成矩阵并且设置有通常连接到相应列的存储器单元的字线和共同连接到各行的存储单元的位线的虚拟单元部分，虚拟单元部分具有第一组虚拟通过相应的第一电容连接到所述存储单元阵列的相应互补位线对的字线和通过相应的第二电容连接到所述存储单元阵列的相应互补位线对的第二组虚拟字线，线电势控制电路，当所述存储单元阵列的所述字线被激活时，能够可选地控制驱动所选择的虚拟字线的模式，以及连接到所述存储单元阵列的相应互补位线对的读出放大器，用于从所选存储单元读取数据的存储单元阵列到相关位线上。

27. 发明授权

US5138427A Semiconductor device having a particular structure allowing for voltage stress test application 失效
标题翻译：具有电压应力测试应用的特殊结构的半导体器件
公开(公告)号：US5138427A
公开(公告)日：1992-08-11
申请号：US547036
申请日：1990-07-02
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： H01L21/66 , G01R31/28 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , H01L21/768 , H01L21/8242 , H01L23/528 , H01L27/108
CPC分类号： G01R31/2856 , H01L21/76886 , H01L23/528 , G01R31/2831 , G01R31/2863 , H01L2924/0002
摘要： Since the power-supply and/or signal-transmission wiring layers connected to the semiconductor chip regions are formed, each individual integrated circuit can be burned in on the semiconductor wafer and, in other words, an integrated circuit can be burned in on a wafer level. The integrated circuit can thus be burned in at the end of a wafer process. An assembled semiconductor device is subjected to a high temperature or a high humidity, for checking the reliability of the assembled device.

28. 发明授权

US4569036A Semiconductor dynamic memory device 失效
标题翻译：半导体动态存储器件
公开(公告)号：US4569036A
公开(公告)日：1986-02-04
申请号：US470627
申请日：1983-02-28
申请人： Syuso Fujii , Shozo Saito , Kenji Natori , Tohru Furuyama
发明人： Syuso Fujii , Shozo Saito , Kenji Natori , Tohru Furuyama
IPC分类号： G11C11/401 , G11C5/02 , G11C8/00 , G11C11/407 , G11C11/408 , G11C11/4091 , G11C11/4096 , G11C13/00
CPC分类号： G11C11/4091 , G11C11/407 , G11C11/408 , G11C11/4087 , G11C11/4096 , G11C5/025
摘要： A semiconductor dynamic memory device includes a plurality of memories, row decoders for selecting the row of the memories, column decoders for selecting the column of memories, and sense amplifier circuits connected to the memories, respectively. The dynamic memory device further has a driving circuit for selectively activating some of the sense amplifier circuits in accordance with the content of a predetermined bit of row address data supplied to the row decoders.
摘要翻译：半导体动态存储器件包括多个存储器，用于选择存储器行的行解码器，用于选择存储器列的列解码器，以及连接到存储器的读出放大器电路。动态存储装置还具有用于根据提供给行解码器的行地址数据的预定位的内容选择性地激活一些读出放大器电路的驱动电路。

29. 发明授权

US4404657A Semiconductor memory circuit 失效
标题翻译：半导体存储电路
公开(公告)号：US4404657A
公开(公告)日：1983-09-13
申请号：US197564
申请日：1980-10-16
申请人： Tohru Furuyama , Tetsuya Iizuka
发明人： Tohru Furuyama , Tetsuya Iizuka
IPC分类号： G11C11/41 , G11C8/16 , G11C11/412 , G11C11/40
CPC分类号： G11C8/16
摘要： A semiconductor memory circuit includes a power supply terminal; a first MOS transistor; a second MOS transistor whose source, gate and drain are respectively connected to the source, drain and gate of the first MOS transistor; first and second resistors connected between the power supply terminal and the drains of the first and second MOS transistors; a data line; a word line; and a third MOS transistor whose current path is connected between the drain of the first MOS transistor and data line, and whose gate is connected to the word line. The semiconductor memory circuit further includes a write control line whose potential is set at a high level when a readout operation is effected. The sources of the first and second MOS transistors are jointly connected to the write control line.
摘要翻译：半导体存储电路包括电源端子; 第一MOS晶体管; 源极，栅极和漏极分别连接到第一MOS晶体管的源极，漏极和栅极的第二MOS晶体管; 连接在电源端子和第一和第二MOS晶体管的漏极之间的第一和第二电阻器; 数据线字线以及第三MOS晶体管，其电流路径连接在第一MOS晶体管的漏极和数据线之间，其栅极连接到字线。半导体存储电路还包括当执行读出操作时其电位被设置为高电平的写入控制线。第一和第二MOS晶体管的源极共同连接到写入控制线。

30. 发明授权

US4398267A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4398267A
公开(公告)日：1983-08-09
申请号：US212103
申请日：1980-12-02
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： G11C11/404 , G11C11/405 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/10 , H01L27/108 , H01L29/04 , H01L29/08 , H01L29/78 , G11C11/40
CPC分类号： G11C11/405 , G11C11/404 , H01L27/108 , H01L29/04 , H01L29/0847
摘要： A plurality of memory cells are arranged on a semiconductor substrate in the matrix form. Each memory cell comprises a first MOS field effect transistor whose drain electrode is connected to a read bit line, and whose source electrode is connected to a read word line, and a second MOS field effect transistor whose source electrode is connected to the gate electrode of the first MOS field effect transistor, and whose drain electrode is connected to a write bit line, and whose gate electrode is connected to a write word line. The first MOS field effect transistor is formed in the surface region of the semiconductor substrate and the second MOS field effect transistor is formed of a polycrystalline silicon layer, which is deposited on the semiconductor substrate with an oxide layer interposed therebetween to act as the gate region of the first MOS field effect transistor.
摘要翻译：多个存储单元以矩阵形式布置在半导体衬底上。每个存储单元包括第一MOS场效应晶体管，其漏电极连接到读位线，并且其源电极连接到读字线;以及第二MOS场效应晶体管，其源极连接到栅电极第一MOS场效应晶体管，其漏电极连接到写位线，并且其栅电极连接到写字线。第一MOS场效应晶体管形成在半导体衬底的表面区域中，第二MOS场效应晶体管由多晶硅层形成，多晶硅层沉积在半导体衬底上，氧化层插入其间用作栅极区的第一MOS场效应晶体管。

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