专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07454345B2 Word or collocation emphasizing voice synthesizer 有权
标题翻译：词或搭配强调语音合成器
公开(公告)号：US07454345B2
公开(公告)日：2008-11-18
申请号：US11063758
申请日：2005-02-23
申请人： Hitoshi Sasaki , Yasushi Yamazaki , Yasuji Ota , Kaori Endo , Nobuyuki Katae , Kazuhiro Watanabe
发明人： Hitoshi Sasaki , Yasushi Yamazaki , Yasuji Ota , Kaori Endo , Nobuyuki Katae , Kazuhiro Watanabe
IPC分类号： G10L13/00
CPC分类号： G10L13/08 , G10L13/04 , G10L13/10
摘要： A voice synthesizer, which obtains a voice by emphasizing a specific part of a sentence, includes an emphasis degree deciding unit that extracts a word or a collocation to be emphasized from among respective words or respective collocations on the basis of an extracting reference with respect to the each word or the each collocation included in a sentence and deciding an emphasis degree of the extracted word or the extracted collocation, an acoustic processing unit that synthesizes a voice having an emphasis degree which is decided by the emphasis degree deciding unit applied to the word to be emphasized or the collocation to be emphasized, whereby the emphasized part of the word or the collocation can be obtained automatically on the basis of the extracting reference, such as a frequency of appearance and a level of importance of the word or the collocation.
摘要翻译：通过强调句子的特定部分来获取语音的语音合成器包括：强调度决定单元，其基于相对于所述语句的提取参考，从各个单词或各个搭配中提取要强调的单词或搭配包括在句子中的每个单词或每个搭配，并且决定所提取的单词或所提取的搭配的强调程度;声学处理单元，其将由强调度决定单元决定的强调度的声音合成到该单词中要强调的搭配，或者要强调的搭配，从而可以基于提取参考（例如出现的频率和单词的重要性或搭配的水平）自动获得单词或搭配的强调部分。

22. 发明申请

US20080111196A1 Semiconductor device having a contact pad 失效
标题翻译：具有接触垫的半导体器件
公开(公告)号：US20080111196A1
公开(公告)日：2008-05-15
申请号：US11598644
申请日：2006-11-14
申请人： Yasushi Yamazaki
发明人： Yasushi Yamazaki
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/76897 , H01L27/10873 , H01L29/6659
摘要： A DRAM device includes contact pads having a bottom in contact with a corresponding source/drain region 21 and a top in contact with a bottom of an overlying contact plug. The source/drain region has a recess caused by misalignment of the contact pad with respect to the source/drain region, the recess causing division of the original source/drain region. An additional diffused region is formed by ion-implantation to couple the divided source/drain region to reduce the junction leakage current flowing across the source/drain region.
摘要翻译： DRAM器件包括具有与相应的源极/漏极区域21接触的底部的接触焊盘和与上覆接触插头的底部接触的顶部。源极/漏极区域具有由接触焊盘相对于源极/漏极区域的不对准引起的凹部，该凹部引起原始源极/漏极区域的划分。通过离子注入形成附加的扩散区域以耦合分割的源极/漏极区域以减少流过源极/漏极区域的结漏电流。

23. 发明授权

US07203326B2 Noise suppressing apparatus 有权
标题翻译：噪声抑制装置
公开(公告)号：US07203326B2
公开(公告)日：2007-04-10
申请号：US10113636
申请日：2002-03-27
申请人： Hitoshi Matsuzawa , Yasushi Yamazaki
发明人： Hitoshi Matsuzawa , Yasushi Yamazaki
IPC分类号： H04B15/00
CPC分类号： G10L21/0208
摘要： In an apparatus which estimates characteristics of a surrounding noise only when an input signal is soundless and performs a noise reduction or suppression of the input signal based on the estimated result, a signal noise ratio is estimated from the input signal, and an automatic switch or an automatic adjustment is performed so as to execute a noise reduction only when the signal noise ratio is good, otherwise to avoid the noise reduction or make the noise reduction degree smaller.
摘要翻译：在仅在输入信号无声并且基于估计结果执行噪声降低或抑制输入信号的情况下估计周围噪声的特性的装置中，根据输入信号和自动切换或执行自动调整，以便仅当信号噪声比良好时执行噪声降低，否则避免噪声降低或降低噪声。

24. 发明申请

US20070059871A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070059871A1
公开(公告)日：2007-03-15
申请号：US11519818
申请日：2006-09-13
申请人： Yasushi Yamazaki
发明人： Yasushi Yamazaki
IPC分类号： H01L21/8234
CPC分类号： H01L21/823481 , H01L27/10876 , H01L29/66621
摘要： In a method of manufacturing a semiconductor device, a recess is formed in a semiconductor substrate. A gate insulating film is formed on a surface of the semiconductor substrate and a surface of the recess; and a gate electrode film is deposited on the gate insulating film to fill the recess. Then, a gate electrode is formed by etching the gate electrode film by using a predetermined mask, and ion implantation into the semiconductor substrate is carried out to form diffusion layers extending from the recess, before the forming a gate electrode at least.
摘要翻译：在制造半导体器件的方法中，在半导体衬底中形成凹部。在半导体衬底的表面和凹部的表面上形成栅极绝缘膜; 并且在栅极绝缘膜上沉积栅极电极膜以填充凹部。然后，通过使用预定的掩模蚀刻栅极电极膜来形成栅电极，并且至少在形成栅电极之前，进行到半导体衬底的离子注入以形成从凹部延伸的扩散层。

25. 发明授权

US07039903B2 Method of and device for collating data, and computer product 失效
标题翻译：数据整理方法和设备，电脑产品
公开(公告)号：US07039903B2
公开(公告)日：2006-05-02
申请号：US09983370
申请日：2001-10-24
申请人： Takeshi Otani , Yasushi Yamazaki , Hitoshi Sasaki
发明人： Takeshi Otani , Yasushi Yamazaki , Hitoshi Sasaki
IPC分类号： G06F9/44
CPC分类号： G06N99/005
摘要： The collating device includes the Formant estimation section that estimates feature amount data that represents a time-based change in frequencies of first and second Formants from voice data input through the microphone. The difference computing section calculates a difference between some reference feature amount data and the feature amount data as the feature-amount difference data. This feature-amount difference data is stored in a database. The feature-amount difference data corresponding to voice data input upon collation is collated with the feature-amount difference data registered in the database, and the result is output.
摘要翻译：对照装置包括共振峰估计部分，其从通过麦克风输入的语音数据估计表示第一和第二共振峰的频率基于时间的变化的特征量数据。差分计算部分计算一些参考特征量数据和特征量数据之间的差作为特征量差异数据。该特征量差异数据存储在数据库中。对应于在核对中输入的语音数据的特征量差分数据与登记在数据库中的特征量差异数据进行对照，并输出结果。

26. 发明授权

US06770555B2 Process for fabricating semiconductor integrated circuit device having polycide line and impurity region respectively exposed to contact holes different in depth 失效
标题翻译：具有分别暴露于深度不同的接触孔的具有多晶硅线和杂质区的半导体集成电路器件的工艺
公开(公告)号：US06770555B2
公开(公告)日：2004-08-03
申请号：US09247926
申请日：1999-02-11
申请人： Yasushi Yamazaki
发明人： Yasushi Yamazaki
IPC分类号： H01L214763
CPC分类号： H01L27/10888 , H01L21/31116 , H01L21/32137 , H01L21/76802 , H01L27/10814 , H01L27/10894
摘要： When contact holes are concurrently formed in an inter-level insulating layer over an impurity region in a silicon substrate and a polycide line on a thick field oxide layer, the manufacturer interrupts the etching at the refractory metal silicide layer of the polycide line, and restarts the etching after removal of a part of the refractory metal silicide layer exposed to the short contact hole, thereby preventing the impurity region from undesirable etching for the refractory metal silicide layer.
摘要翻译：当接触孔同时形成在硅衬底中的杂质区域和厚场氧化物层上的多晶硅化物层之间的层间绝缘层中时，制造商中断多晶硅化物线的难熔金属硅化物层处的蚀刻，并重新开始在去除暴露于短接触孔的难熔金属硅化物层的一部分之后的蚀刻，从而防止杂质区域对难熔金属硅化物层的不希望的蚀刻。

27. 发明授权

US06768522B2 Electrooptical device, prejection-type display apparatus, and method for manufacturing the electrooptical device 失效
标题翻译：电光装置，预想型显示装置以及电光装置的制造方法
公开(公告)号：US06768522B2
公开(公告)日：2004-07-27
申请号：US10428988
申请日：2003-05-05
申请人： Masahiro Yasukawa , Yasushi Yamazaki
发明人： Masahiro Yasukawa , Yasushi Yamazaki
IPC分类号： G02F11368
CPC分类号： G02F1/136209 , G02F1/133553 , G02F1/136227 , G02F1/1368 , H01L29/78633
摘要： In a TFT array substrate 10 of an electrooptical device, a scanning line 3a, a drain electrode 11, a first light shield layer 13, and a data line 3a are laminated over a channel region 1a′ of a TFT 30 and a second light shield layer 14 is laminated beneath the channel region 1a′. A side wall formation trench 16 is formed beside the channel region 1a′ of the TFT 30, and in the side wall formation trench a conductive layer having a light shield property is concurrently formed with the first light shield layer 13 thereby a light shield side wall 131 is formed. By three-dimensionally blocking light's entry towards the channel region 1a′, obliquely or laterally incident light is prevented from entering the channel region of a pixel switching TFT, and the TFT 30 is free from erratic operations and reliability degradation.
摘要翻译：在电光装置的TFT阵列基板10中，扫描线3a，漏电极11，第一遮光层13和数据线3a层叠在TFT 30的通道区域1a'和第二遮光板层14层叠在通道区域1a'的下方。在TFT30的沟道区域1a'旁边形成有侧壁形成沟槽16，并且在侧壁形成沟槽中，与第一遮光层13同时形成具有遮光性的导电层，从而形成遮光侧壁 131形成。通过三维地阻挡光线朝向沟道区域1a'的入射，防止了倾斜或侧向入射的光进入像素开关TFT的沟道区域，并且TFT 30没有不稳定的操作和可靠性降低。

28. 发明授权

US5474948A Method of making semiconductor device having polysilicon resistance element 失效
标题翻译：制造具有多晶硅电阻元件的半导体器件的方法
公开(公告)号：US5474948A
公开(公告)日：1995-12-12
申请号：US994095
申请日：1992-12-18
申请人： Yasushi Yamazaki
发明人： Yasushi Yamazaki
IPC分类号： H01L21/02 , H01L21/8244 , H01L27/11 , H01L21/70
CPC分类号： H01L28/20 , H01L27/11 , H01L27/1112 , Y10S148/136 , Y10S257/903 , Y10S257/904
摘要： A polysilicon resistor element and a semiconductor device using the same are disclosed. The polysilicon resistor element has a resistive polysilicon film formed on a predetermined interlayer insulating film of a semiconductor chip. The resistive polysilicon film is covered by an insulating film having holes and high melting point metal films are formed in self-alignment to the holes. The high melting metal film constitutes one of lead portions of the polysilicon resistor element. A diffusion of the high melting point metal film due to heat treatment during fabrication, which causes an effective length of the resistor element, becomes negligible and reproducibility is improved.
摘要翻译：公开了一种多晶硅电阻元件和使用其的半导体器件。多晶硅电阻元件具有形成在半导体芯片的预定层间绝缘膜上的电阻多晶硅膜。电阻性多晶硅膜由具有孔的绝缘膜覆盖，并且高熔点金属膜形成为与孔自对准。高熔点金属膜构成多晶硅电阻元件的引线部分之一。在制造期间由于热处理引起的高熔点金属膜的扩散，导致电阻元件的有效长度变得可忽略，并且再现性得到改善。

29. 发明授权

US5352916A Fully CMOS-type SRAM device with grounding wire having contact holes 失效
标题翻译：具有接地孔的完全CMOS型SRAM器件
公开(公告)号：US5352916A
公开(公告)日：1994-10-04
申请号：US936336
申请日：1992-08-28
申请人： Junji Kiyono , Yasushi Yamazaki
发明人： Junji Kiyono , Yasushi Yamazaki
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/78 , H01L29/786 , H01L27/04
CPC分类号： H01L27/1108 , Y10S257/903
摘要： A grounding wiring layer is provided on the substantially entire region between driver MOS transistors and load MOS thin film transistors of a flip-flop type memory cell. The contact holes for connecting the gate electrodes of the MOS thin film transistors with storage nodes are formed by providing a side wall on the inner wall of each of the contact hole portions formed in the grounding wiring layer and inter-layer insulating films sandwiching it. Thus, the impedance of the grounding wiring layer can be reduced to stabilize the operation of a miniaturized SRAM memory cell using the load MOS thin film transistors. The resistance against soft error caused by .alpha.-ray can also be improved.
摘要翻译：在触发型存储单元的驱动MOS晶体管和负载MOS薄膜晶体管之间的大致整个区域上设置接地布线层。用于将MOS薄膜晶体管的栅电极与存储节点连接的接触孔通过在形成在接地布线层中的每个接触孔部分的内壁上设置侧壁和夹在其上的层间绝缘膜来形成。因此，可以减小接地布线层的阻抗，以稳定使用负载MOS薄膜晶体管的小型化的SRAM存储单元的工作。也可以提高由alpha -ray引起的对软误差的抵抗力。

30. 发明申请

US20150364475A1 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150364475A1
公开(公告)日：2015-12-17
申请号：US14762527
申请日：2014-01-17
申请人： Yasushi Yamazaki
发明人： Yasushi Yamazaki
IPC分类号： H01L27/108 , H01L29/08 , H01L29/423 , H01L27/02 , H01L29/06
CPC分类号： H01L27/10823 , H01L27/0207 , H01L27/10814 , H01L27/10876 , H01L29/0649 , H01L29/0847 , H01L29/4236
摘要： One semiconductor device includes a plurality of first element-separating regions formed on a semiconductor substrate so as to extend along a first direction (Y direction), a plurality of second element-separating regions formed so as to extend along a second direction (X direction) that intersects with the first direction (Y direction), a plurality of active regions insulated and separated by the first element-separating regions and the second element-separating regions a plurality of gate electrodes (word lines) formed so as to extend along the first direction (Y direction), and an embedded diffusion layer that is formed in a position deeper than the first element-separating regions and the second element-separating regions, and that has an inverse characteristic to the active regions.
摘要翻译：一个半导体器件包括形成在半导体衬底上以沿第一方向（Y方向）延伸的多个第一元件分离区域，形成为沿第二方向（X方向）延伸的多个第二元件分离区域），与第一方向（Y方向）相交的多个有源区域，被第一元件分离区域和第二元件分离区域绝缘和分离的多个有源区域，形成为沿着第一方向（Y方向）和形成在比第一元件分离区域和第二元件分离区域更深的位置的嵌入式扩散层，并且具有与有源区域相反的特性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式