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21. 发明授权

US07983086B2 NAND flash memory 失效
标题翻译： NAND闪存
公开(公告)号：US07983086B2
公开(公告)日：2011-07-19
申请号：US12564598
申请日：2009-09-22
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： G11C16/00
CPC分类号： G11C11/5628 , G11C16/0483
摘要： In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the memory cell transistors and which is to be cut off, a second voltage which is higher than the first voltage and which causes a plurality of third memory cell transistors remaining unselected in the memory cell transistors to conduct is applied to control gates of the third memory cell transistors, and thereafter a threshold voltage of the first memory cell transistor is changed to a threshold voltage higher than the first threshold voltage corresponding to the erase state by applying a third voltage which is higher than the second voltage to a control gate of the first memory cell transistor.
摘要翻译：在第一和第二选择栅极晶体管被截止并且第一电压被施加到第二存储单元晶体管的控制栅极的状态下，第二存储单元晶体管连接到从存储器中选择的第一存储单元晶体管的源极线侧单元晶体管并且要被切断，高于第一电压的第二电压并且使得在存储单元晶体管导通时保持未选择的多个第三存储单元晶体管被施加到第三存储单元晶体管的控制栅极之后，通过向第一存储单元的控制栅极施加高于第二电压的第三电压，将第一存储单元晶体管的阈值电压改变为高于与擦除状态相对应的第一阈值电压的阈值电压晶体管。

22. 发明申请

US20100173471A1 NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20100173471A1
公开(公告)日：2010-07-08
申请号：US12720062
申请日：2010-03-09
申请人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
发明人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧道绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层和第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层和第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅极电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在存储单元晶体管的第一源极和漏极区域，低压晶体管的第二源极和漏极区域以及高压晶体管的第三源极和漏极区域中的衬垫绝缘膜。

23. 发明授权

US07705394B2 Nonvolatile semicondutor memory with metallic silicide film electrically connected to a control gate electrode layer 失效
标题翻译：非易失性半导体存储器，其与金属硅化物膜电连接到控制栅电极层
公开(公告)号：US07705394B2
公开(公告)日：2010-04-27
申请号：US11553661
申请日：2006-10-27
申请人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
发明人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on first, second and third source and drain regions of the memory cell transistor, low voltage transistor, and high voltage transistor, respectively.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧穿绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层以及第一金属硅化物膜; 包括形成在高电压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层以及第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅电极层和第三金属硅化物膜的低压晶体管; 以及分别直接设置在存储单元晶体管，低压晶体管和高压晶体管的第一，第二和第三源极和漏极区上的衬垫绝缘膜。

24. 发明授权

US07663178B2 Nonvolatile semiconductor memory with resistance elements and method of manufacturing the same 失效
标题翻译：具有电阻元件的非易失性半导体存储器及其制造方法
公开(公告)号：US07663178B2
公开(公告)日：2010-02-16
申请号：US11850978
申请日：2007-09-06
申请人： Fumitaka Arai , Atsuhiro Sato
发明人： Fumitaka Arai , Atsuhiro Sato
IPC分类号： H01L29/72
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11539 , H01L29/78
摘要： A nonvolatile semiconductor memory of an aspect of the present invention comprises a memory cell transistor and a resistance element arranged on a semiconductor substrate. The memory cell transistor includes a floating gate electrode constituted of a first conductive material arranged on a gate insulating film on a surface of the semiconductor substrate, an inter-gate insulating film arranged on the floating gate electrode, a control gate electrode arranged on the inter-gate insulating film, and a source/drain diffusion layer provided in the semiconductor substrate. The resistance element includes an element isolation insulating layer arranged in the semiconductor substrate and including a depression, and a resistor constituted of a second conductive material filling up the depression. An impurity concentration of the second conductive material is lower than that of the first conductive material.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括存储单元晶体管和布置在半导体衬底上的电阻元件。存储单元晶体管包括由在半导体衬底的表面上配置在栅极绝缘膜上的第一导电材料构成的浮置栅极电极，布置在浮置栅电极上的栅极间绝缘膜，栅极绝缘膜和设置在半导体衬底中的源极/漏极扩散层。电阻元件包括布置在半导体衬底中并包括凹陷的元件隔离绝缘层和由填充凹陷的第二导电材料构成的电阻器。第二导电材料的杂质浓度低于第一导电材料的杂质浓度。

25. 发明申请

US20080121965A1 NONVOLATILE SEMICONDUCTOR MEMORY 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20080121965A1
公开(公告)日：2008-05-29
申请号：US11870114
申请日：2007-10-10
申请人： Atsuhiro SATO , Fumitaka Arai , Yasuhiko Matsunaga
发明人： Atsuhiro SATO , Fumitaka Arai , Yasuhiko Matsunaga
IPC分类号： H01L27/105
CPC分类号： H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory of an aspect of the present invention comprises a plurality of memory cell transistors which are connected in series to one another with a first gate spacing, every two adjacent transistors of the memory cell transistors sharing a source/drain diffusion layer, and a first select gate transistor which shares a source/drain diffusion layer with an endmost memory cell transistor that is located at one end of the series connection of the memory cell transistors and is adjacent to that memory cell transistor with a second gate spacing. The second gate spacing is set larger than the first gate spacing and the source/drain diffusion layer shared by the endmost memory cell transistor and the first select gate transistor contains a region which is higher in impurity concentration than the source/drain diffusion layer shared by two adjacent memory cell transistors.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括以第一栅极间隔彼此串联连接的多个存储单元晶体管，存储单元晶体管的每两个相邻晶体管共享源极/漏极扩散层，以及共享源/漏扩散层的第一选择栅极晶体管，其具有位于存储单元晶体管的串联连接的一端并且具有第二栅极间隔的该存储单元晶体管的最末端的存储单元晶体管。第二栅极间隔被设定为大于第一栅极间隔，并且由最末端存储单元晶体管共享的源极/漏极扩散层，并且第一选择栅极晶体管包含杂质浓度高于源极/漏极扩散层所分配的源极/漏极扩散层的区域两个相邻的存储单元晶体管。

26. 发明申请

US20070177431A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20070177431A1
公开(公告)日：2007-08-02
申请号：US11447963
申请日：2006-06-07
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.
摘要翻译：公开了一种包括具有多个块的存储单元阵列的半导体集成电路器件，布置在存储单元阵列中并具有电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体存储单元，布置在与第一非易失性半导体存储单元相邻的存储单元阵列中，并具有电荷存储层。在相对于第一非易失性半导体存储单元执行常规数据写入之后，相对于第二非易失性半导体存储单元执行正常数据写入。在相对于第二非易失性半导体存储单元执行常规数据写入之后，相对于第一非易失性半导体存储单元执行附加数据写入。

27. 发明申请

US20060097307A1 Nonvolatile semiconductor memory and manufacturing method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US20060097307A1
公开(公告)日：2006-05-11
申请号：US11311262
申请日：2005-12-20
申请人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
发明人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529
摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.
摘要翻译：存储单元晶体管具有第一单元位置栅绝缘体，第一单元位栅极绝缘体上的第一下导电层，第一下导电层上的第一电极间电介质，以及第一电极上的第一上导电层电介质。选择晶体管具有与第一单元位置栅绝缘体相同厚度的第二单元位栅极绝缘体，第二单元位栅极绝缘体上的第二下导电层，第二下导电层上的第二电极间电介质，以及在第二电极间电介质上的第二上导电层。外围晶体管具有第一外围栅极绝缘体，该第一外围栅极绝缘体具有比第一栅极绝缘体更薄的厚度。

28. 发明授权

US07012295B2 Semiconductor memory with peripheral transistors having gate insulator thickness being thinner than thickness of memory and select transistors 失效
标题翻译：具有栅极绝缘体厚度的外围晶体管的半导体存储器比存储器和选择晶体管的厚度更薄
公开(公告)号：US07012295B2
公开(公告)日：2006-03-14
申请号：US10878372
申请日：2004-06-29
申请人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
发明人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529
摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.
摘要翻译：存储单元晶体管具有第一单元位置栅绝缘体，第一单元位栅极绝缘体上的第一下导电层，第一下导电层上的第一电极间电介质，以及第一电极上的第一上导电层电介质。选择晶体管具有与第一单元位置栅绝缘体相同厚度的第二单元位栅极绝缘体，第二单元位栅极绝缘体上的第二下导电层，第二下导电层上的第二电极间电介质，以及在第二电极间电介质上的第二上导电层。外围晶体管具有第一外围栅极绝缘体，该第一外围栅极绝缘体具有比第一栅极绝缘体更薄的厚度。

29. 发明申请

US20050105336A1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20050105336A1
公开(公告)日：2005-05-19
申请号：US10944940
申请日：2004-09-21
申请人： Atsuhiro Sato , Yasuhiko Matsunaga , Fumitaka Arai
发明人： Atsuhiro Sato , Yasuhiko Matsunaga , Fumitaka Arai
IPC分类号： G11C16/06 , G11C11/34 , G11C16/04 , G11C16/12 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/12 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： A semiconductor memory includes a memory cell array having a memory cell units, configured from memory cell transistors connected in a column, which have a first and a second control gate disposed on both sides of a floating gate horizontally arranged with a first end connected to a bit line via a first select-gate transistor, and a second end connected to a source line via a second select-gate transistor. The first and the second control gate of memory cell transistors arranged in the same row are connected in common to a first and a second control gate line in a row, respectively. It also includes a boosting circuit, which generates a write-in voltage, multilevel intermediate voltages, and a bit line voltage from a power source, and a row decoder supplied with the write-in voltage and the multilevel intermediate voltages to select the first and the second control gate.
摘要翻译：半导体存储器包括具有存储单元单元的存储单元阵列，存储单元单元由连接在列中的存储单元晶体管构成，其具有设置在浮置栅极两侧的第一和第二控制栅极，水平布置，第一端连接到经由第一选择栅晶体管的位线，以及经由第二选择栅极晶体管连接到源极线的第二端。布置在同一行中的存储单元晶体管的第一和第二控制栅极分别连接到一行中的第一和第二控制栅极线。它还包括升压电路，其从电源产生写入电压，多电平中间电压和位线电压，以及提供有写入电压和多电平中间电压的行解码器，以选择第一和第二控制门。

30. 发明申请

US20120094461A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120094461A1
公开(公告)日：2012-04-19
申请号：US13332462
申请日：2011-12-21
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L21/8234
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11529
摘要： First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode.
摘要翻译：存储单元晶体管的第一栅电极在半导体衬底上彼此串联形成。第一选择晶体管的第二栅电极与第一电极的一端相邻地形成。第二选择晶体管的第三栅电极与第二电极相邻地形成。在基板上形成周边晶体管的第四栅电极。第一，第二和第三侧壁膜分别形成在第二，第三和第四栅电极的侧表面上。第三侧壁膜的膜厚大于第一和第二侧壁膜的膜厚。第一电极和第二电极之间的空间大于第一电极之间的空间，并且第二电极和第三电极之间的间隔大于第一电极和第二电极之间的间隔。

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