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21. 发明授权

US07904657B2 Cache residence prediction 有权
标题翻译：缓存居住预测
公开(公告)号：US07904657B2
公开(公告)日：2011-03-08
申请号：US11779749
申请日：2007-07-18
申请人： Xiaowei Shen , Jaehyuk Huh , Balaram Sinharoy
发明人： Xiaowei Shen , Jaehyuk Huh , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0893 , G06F2212/507
摘要： The present invention proposes a novel cache residence prediction mechanism that predicts whether requested data of a cache miss can be found in another cache. The memory controller can use the prediction result to determine if it should immediately initiate a memory access, or initiate no memory access until a cache snoop response shows that the requested data cannot be supplied by a cache.The cache residence prediction mechanism can be implemented at the cache side, the memory side, or both. A cache-side prediction mechanism can predict that data requested by a cache miss can be found in another cache if the cache miss address matches an address tag of a cache line in the requesting cache and the cache line is in an invalid state. A memory-side prediction mechanism can make effective prediction based on observed memory and cache operations that are recorded in a prediction table.
摘要翻译：本发明提出了一种新颖的缓存驻留预测机制，其预测是否可以在另一个高速缓存中找到所请求的高速缓存未命中的数据。存储器控制器可以使用预测结果来确定它是否应该立即启动存储器访问，或者不启动存储器访问，直到高速缓存侦听响应显示所请求的数据不能被高速缓存提供。缓存驻留预测机制可以在高速缓存侧，存储器侧或两者中实现。如果高速缓存未命中地址与请求高速缓存中的高速缓存线的地址标签匹配并且高速缓存行处于无效状态，则高速缓存侧预测机制可以预测在另一个高速缓存中可以找到由高速缓存未命中请求的数据。存储器侧预测机制可以基于记录在预测表中的观察到的存储器和高速缓存操作来进行有效的预测。

22. 发明申请

US20090024797A1 Cache Residence Prediction 有权
标题翻译：缓存住宅预测
公开(公告)号：US20090024797A1
公开(公告)日：2009-01-22
申请号：US11779749
申请日：2007-07-18
申请人： Xiaowei Shen , Jaehyuk Huh , Balaram Sinharoy
发明人： Xiaowei Shen , Jaehyuk Huh , Balaram Sinharoy
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0893 , G06F2212/507
摘要： The present invention proposes a novel cache residence prediction mechanism that predicts whether requested data of a cache miss can be found in another cache. The memory controller can use the prediction result to determine if it should immediately initiate a memory access, or initiate no memory access until a cache snoop response shows that the requested data cannot be supplied by a cache.The cache residence prediction mechanism can be implemented at the cache side, the memory side, or both. A cache-side prediction mechanism can predict that data requested by a cache miss can be found in another cache if the cache miss address matches an address tag of a cache line in the requesting cache and the cache line is in an invalid state. A memory-side prediction mechanism can make effective prediction based on observed memory and cache operations that are recorded in a prediction table.
摘要翻译：本发明提出了一种新颖的缓存驻留预测机制，其预测是否可以在另一个高速缓存中找到所请求的高速缓存未命中的数据。存储器控制器可以使用预测结果来确定它是否应该立即启动存储器访问，或者不启动存储器访问，直到高速缓存侦听响应显示所请求的数据不能被高速缓存提供。缓存驻留预测机制可以在高速缓存侧，存储器侧或两者中实现。如果高速缓存未命中地址与请求高速缓存中的高速缓存行的地址标签匹配并且高速缓存行处于无效状态，则高速缓存侧预测机制可以预测在另一个高速缓存中可以发现由高速缓存未命中请求的数据。存储器侧预测机制可以基于记录在预测表中的观察到的存储器和高速缓存操作来进行有效的预测。

23. 发明申请

US20080263284A1 Methods and Arrangements to Manage On-Chip Memory to Reduce Memory Latency 有权
标题翻译：管理片上存储器以减少内存延迟的方法和布置
公开(公告)号：US20080263284A1
公开(公告)日：2008-10-23
申请号：US12145034
申请日：2008-06-24
申请人： Dilma Menezes da Silva , Elmootazbellah Nabil Elnozahy , Orran Yaakov Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Brett Tremaine
发明人： Dilma Menezes da Silva , Elmootazbellah Nabil Elnozahy , Orran Yaakov Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0893 , G06F2212/251 , G06F2212/253
摘要： Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.
摘要翻译：考虑通过操作系统提供对软件应用（OCM）的控制的措施来减少处理器所看到的存储器延迟的方法，系统和媒体。许多实施例允许OCM的一部分由软件应用程序通过应用程序接口（API）和由硬件管理的部分来管理。因此，软件应用程序可以提供关于地址范围的指导，以保持靠近处理器，以减少在依赖于缓存控制器策略时通常遇到的不必要的延迟。几个实施例利用处理器内部或处理器节点上的存储器，因此用于该技术的存储器块被称为OCM。

24. 发明授权

US07437517B2 Methods and arrangements to manage on-chip memory to reduce memory latency 有权
标题翻译：管理片上存储器以减少内存延迟的方法和安排
公开(公告)号：US07437517B2
公开(公告)日：2008-10-14
申请号：US11032876
申请日：2005-01-11
申请人： Dilma Menezes da Silva , Elmootazbellah Nabil Elnozahy , Orran Yaakov Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Brett Tremaine
发明人： Dilma Menezes da Silva , Elmootazbellah Nabil Elnozahy , Orran Yaakov Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F12/00 , G06F13/00 , G06F3/00
CPC分类号： G06F12/08 , G06F12/0893 , G06F2212/251 , G06F2212/253
摘要： Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.
摘要翻译：考虑通过操作系统提供对软件应用（OCM）的控制的措施来减少处理器所看到的存储器延迟的方法，系统和媒体。许多实施例允许OCM的一部分由软件应用程序通过应用程序接口（API）和由硬件管理的部分来管理。因此，软件应用程序可以提供关于地址范围的指导，以保持靠近处理器，以减少在依赖于缓存控制器策略时通常遇到的不必要的延迟。几个实施例利用处理器内部或处理器节点上的存储器，因此用于该技术的存储器块被称为OCM。

25. 发明申请

US20050240735A1 Location-aware cache-to-cache transfers 失效
标题翻译：位置感知缓存到缓存传输
公开(公告)号：US20050240735A1
公开(公告)日：2005-10-27
申请号：US10833197
申请日：2004-04-27
申请人： Xiaowei Shen , Jaehyuk Huh , Balaram Sinharoy
发明人： Xiaowei Shen , Jaehyuk Huh , Balaram Sinharoy
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813 , Y02D10/13
摘要： In shared-memory multiprocessor systems, cache interventions from different sourcing caches can result in different cache intervention costs. With location-aware cache coherence, when a cache receives a data request, the cache can determine whether sourcing the data from the cache will result in less cache intervention cost than sourcing the data from another cache. The decision can be made based on appropriate information maintained in the cache or collected from snoop responses from other caches. If the requested data is found in more than one cache, the cache that has or likely has the lowest cache intervention cost is generally responsible for supplying the data. The intervention cost can be measured by performance metrics that include, but are not limited to, communication latency, bandwidth consumption, load balance, and power consumption.
摘要翻译：在共享内存多处理器系统中，来自不同采购缓存的缓存干预可能导致不同的缓存干预成本。利用位置感知高速缓存一致性，当缓存接收到数据请求时，高速缓存可以确定从高速缓存中提取数据是否会导致比从另一高速缓存提供数据更少的高速缓存干预成本。该决定可以基于保存在缓存中的适当信息或从其他缓存的窥探响应收集。如果在多个缓存中找到所请求的数据，则具有或可能具有最低缓存干预成本的高速缓存通常负责提供数据。干预成本可以通过包括但不限于通信延迟，带宽消耗，负载平衡和功耗的性能指标来衡量。

26. 发明授权

US07676637B2 Location-aware cache-to-cache transfers 失效
标题翻译：位置感知缓存到缓存传输
公开(公告)号：US07676637B2
公开(公告)日：2010-03-09
申请号：US10833197
申请日：2004-04-27
申请人： Xiaowei Shen , Jaehyuk Huh , Balaram Sinharoy
发明人： Xiaowei Shen , Jaehyuk Huh , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , Y02D10/13
摘要： In shared-memory multiprocessor systems, cache interventions from different sourcing caches can result in different cache intervention costs. With location-aware cache coherence, when a cache receives a data request, the cache can determine whether sourcing the data from the cache will result in less cache intervention cost than sourcing the data from another cache. The decision can be made based on appropriate information maintained in the cache or collected from snoop responses from other caches. If the requested data is found in more than one cache, the cache that has or likely has the lowest cache intervention cost is generally responsible for supplying the data. The intervention cost can be measured by performance metrics that include, but are not limited to, communication latency, bandwidth consumption, load balance, and power consumption.
摘要翻译：在共享内存多处理器系统中，来自不同采购缓存的缓存干预可能导致不同的缓存干预成本。利用位置感知高速缓存一致性，当缓存接收到数据请求时，高速缓存可以确定从高速缓存中提取数据是否会导致比从另一高速缓存提供数据更少的高速缓存干预成本。该决定可以基于保存在缓存中的适当信息或从其他缓存的窥探响应收集。如果在多个缓存中找到所请求的数据，则具有或可能具有最低缓存干预成本的高速缓存通常负责提供数据。干预成本可以通过包括但不限于通信延迟，带宽消耗，负载平衡和功耗的性能指标来衡量。

27. 发明申请

US20080168239A1 ARCHITECTURE SUPPORT OF MEMORY ACCESS COLORING 有权
标题翻译：存储器访问颜色的架构支持
公开(公告)号：US20080168239A1
公开(公告)日：2008-07-10
申请号：US11620293
申请日：2007-01-05
申请人： Xiaowei Shen , Robert W. Wisniewski , Orran Krieger
发明人： Xiaowei Shen , Robert W. Wisniewski , Orran Krieger
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F12/0862 , G06F12/10 , G06F12/1027
摘要： Memory Access Coloring provides architecture support that allows software to classify memory accesses into different congruence classes by specifying a color for each memory access operation. The color information is received and recorded by the underlying system with appropriate granularity. This allows hardware to monitor color-based cache monitoring information and provide such feedback to the software to enable various runtime optimizations. It also enables enforcement of different memory consistency models for memory regions with different colors at the same time.
摘要翻译：内存访问着色提供架构支持，允许软件通过为每个内存访问操作指定颜色来将内存访问分类为不同的同余类。颜色信息由底层系统以适当的粒度接收和记录。这允许硬件监视基于颜色的缓存监视信息，并向软件提供这样的反馈以启用各种运行时优化。它还可以同时实现具有不同颜色的存储器区域的不同存储器一致性模型。

28. 发明授权

US08799581B2 Cache coherence monitoring and feedback 有权
标题翻译：缓存一致性监控和反馈
公开(公告)号：US08799581B2
公开(公告)日：2014-08-05
申请号：US11620323
申请日：2007-01-05
申请人： Xiaowei Shen , David F. Bacon , Robert W. Wisniewski , Orran Krieger
发明人： Xiaowei Shen , David F. Bacon , Robert W. Wisniewski , Orran Krieger
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/08
CPC分类号： G06F12/0815 , G06F12/0817
摘要： Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads are able to share a cache, effective cache management is critical to overall performance. Color-based caching provides an effective method to better utilize caches and avoid unnecessary cache thrashing and pollution. Hardware maintains color-based counters relative to the cache lines to monitor and obtain feedback on cache line events. These counters are utilized for cache coherence transactions in multiple processor systems.
摘要翻译：基于颜色的缓存允许每个高速缓存行通过特定的颜色进行区分，并且可以基于高速缓存行的颜色来操作缓存行为。当多个线程能够共享缓存时，有效的缓存管理对于整体性能至关重要。基于色彩的缓存提供了一种有效的方法来更好地利用缓存，并避免不必要的缓存颠簸和污染。硬件维护相对于高速缓存行的基于颜色的计数器，以监视和获取有关高速缓存行事件的反馈。这些计数器用于多处理器系统中的高速缓存一致性事务。

29. 发明申请

US20080168237A1 CACHE COHERENCE MONITORING AND FEEDBACK 有权
标题翻译：高速缓存监控和反馈
公开(公告)号：US20080168237A1
公开(公告)日：2008-07-10
申请号：US11620323
申请日：2007-01-05
申请人： Xiaowei Shen , David F. Bacon , Robert W. Wisniewski , Orran Krieger
发明人： Xiaowei Shen , David F. Bacon , Robert W. Wisniewski , Orran Krieger
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0817
摘要： Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads are able to share a cache, effective cache management is critical to overall performance. Color-based caching provides an effective method to better utilize caches and avoid unnecessary cache thrashing and pollution. Hardware maintains color-based counters relative to the cache lines to monitor and obtain feedback on cache line events. These counters are utilized for cache coherence transactions in multiple processor systems.
摘要翻译：基于颜色的缓存允许每个高速缓存行通过特定的颜色进行区分，并且可以基于高速缓存行的颜色来操作缓存行为。当多个线程能够共享缓存时，有效的缓存管理对于整体性能至关重要。基于色彩的缓存提供了一种有效的方法来更好地利用缓存，并避免不必要的缓存颠簸和污染。硬件维护相对于高速缓存行的基于颜色的计数器，以监视和获取有关高速缓存行事件的反馈。这些计数器用于多处理器系统中的高速缓存一致性事务。

30. 发明授权

US07895392B2 Color-based cache monitoring 有权
标题翻译：基于颜色的缓存监控
公开(公告)号：US07895392B2
公开(公告)日：2011-02-22
申请号：US11620348
申请日：2007-01-05
申请人： Xiaowei Shen , David F. Bacon , Robert W. Wisniewski , Orran Krieger
发明人： Xiaowei Shen , David F. Bacon , Robert W. Wisniewski , Orran Krieger
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0842 , G06F12/121
摘要： Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads are able to share a cache, effective cache management is critical to overall performance. Color-based caching provides an effective method to better utilize a cache and avoid unnecessary cache thrashing and/or pollution. The color based caching can be monitored to improve memory performance and guarantee Quality-Of-Service of cache utilization.
摘要翻译：基于颜色的缓存允许每个高速缓存行通过特定的颜色进行区分，并且可以基于高速缓存行的颜色来操作缓存行为。当多个线程能够共享缓存时，有效的缓存管理对于整体性能至关重要。基于色彩的缓存提供了一种更好地利用缓存并避免不必要的缓存颠簸和/或污染的有效方法。可以监控基于颜色的缓存，以提高内存性能，并保证高速缓存利用率的服务质量。

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