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21. 发明授权

US08921918B2 Three-dimensional semiconductor devices 有权
标题翻译：三维半导体器件
公开(公告)号：US08921918B2
公开(公告)日：2014-12-30
申请号：US13280759
申请日：2011-10-25
申请人： Jae-Joo Shim , Kyoung-Hoon Kim , Woonkyung Lee , Wonseok Cho , Hoosung Cho , Jintaek Park , Jong-Yeon Kim , Sung-Min Hwang
发明人： Jae-Joo Shim , Kyoung-Hoon Kim , Woonkyung Lee , Wonseok Cho , Hoosung Cho , Jintaek Park , Jong-Yeon Kim , Sung-Min Hwang
IPC分类号： H01L29/792 , H01L27/115
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.
摘要翻译：可以提供三维半导体器件。这些装置可以包括包括栅极图案和绝缘图案的堆叠结构。堆叠结构还可以包括第一部分和第二部分，并且堆叠结构的第二部分可以具有比第一部分更窄的宽度。装置还可以包括穿透堆叠结构的活动图案。所述装置还可以包括与堆栈结构相邻的公共源区。所述装置还可以包括在公共源区上的捆扎接触塞。

22. 发明授权

US09443863B2 Semiconductor devices 有权
公开(公告)号：US09443863B2
公开(公告)日：2016-09-13
申请号：US14819841
申请日：2015-08-06
申请人： Jeeyong Kim , Woonkyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
发明人： Jeeyong Kim , Woonkyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
IPC分类号： H01L29/49 , H01L27/115 , H01L23/535 , H01L29/78 , H01L21/28 , H01L23/48 , H01L29/788 , H01L29/792 , H01L21/768
CPC分类号： H01L27/11526 , H01L21/28 , H01L21/76841 , H01L23/48 , H01L23/535 , H01L27/11521 , H01L27/11568 , H01L27/11573 , H01L29/4958 , H01L29/78 , H01L29/788 , H01L29/7883 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

23. 发明授权

US09129950B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US09129950B2
公开(公告)日：2015-09-08
申请号：US14568737
申请日：2014-12-12
申请人： Jeeyong Kim , Woonkyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
发明人： Jeeyong Kim , Woonkyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
IPC分类号： H01L29/49 , H01L21/28 , H01L23/48 , H01L29/788 , H01L29/792 , H01L21/768 , H01L27/115
CPC分类号： H01L27/11526 , H01L21/28 , H01L21/76841 , H01L23/48 , H01L23/535 , H01L27/11521 , H01L27/11568 , H01L27/11573 , H01L29/4958 , H01L29/78 , H01L29/788 , H01L29/7883 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.
摘要翻译：提供半导体器件和制造半导体器件的方法。半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。第一浓度可能高于第二浓度。

24. 发明授权

US08476713B2 Vertical-type semiconductor device and method of manufacturing the same 有权
标题翻译：立式半导体器件及其制造方法
公开(公告)号：US08476713B2
公开(公告)日：2013-07-02
申请号：US12588270
申请日：2009-10-09
申请人： Seung-Jun Lee , Woonkyung Lee
发明人： Seung-Jun Lee , Woonkyung Lee
IPC分类号： H01L21/70 , H01L21/336
CPC分类号： H01L27/11551 , H01L27/11526 , H01L27/11529 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A vertical-type semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a wordline structure on the cell region of the semiconductor substrate, the wordline structure including a plurality of wordlines stacked on top of each other, a semiconductor structure through the wordline structure, a gate dielectric between the wordline structure and the semiconductor structure, and a dummy wordline structure on the peripheral circuit region, the dummy wordline structure having a vertical structure and including same components as the wordline structure.
摘要翻译：垂直型半导体器件包括具有单元区域和外围电路区域的半导体衬底，半导体衬底的单元区域上的字线结构，该字线结构包括堆叠在彼此顶部的多个字线，半导体结构通过字线结构，字线结构和半导体结构之间的栅极电介质和外围电路区域上的伪字线结构，虚拟字线结构具有垂直结构并且包括与字线结构相同的部件。

25. 发明申请

US20120098049A1 THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20120098049A1
公开(公告)日：2012-04-26
申请号：US13276682
申请日：2011-10-19
申请人： Hui-Chang MOON , Sung-Min Hwang , Woonkyung Lee
发明人： Hui-Chang MOON , Sung-Min Hwang , Woonkyung Lee
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/11556 , H01L29/7926
摘要： A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.
摘要翻译：三维半导体存储器件具有层叠结构，其包括彼此绝缘的单元栅极和彼此横向分离的第一串选择栅极，延伸穿过第一串选择栅极的垂直有源图案，侧壁之间的多层电介质层垂直有源图案和单元栅极之间以及垂直有源图案和第一串选择栅极的侧壁之间以及至少一个第一补充导电图案。第一串选择栅极设置在单元栅极的最上面的单元栅极上。每个垂直有源图案延伸穿过堆叠在第一串选择门下的每个单元门。第一补充导电图案与第一串选择门之一的侧壁接触。

26. 发明授权

US08395206B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08395206B2
公开(公告)日：2013-03-12
申请号：US13014188
申请日：2011-01-26
申请人： Seung-Jun Lee , Woonkyung Lee
发明人： Seung-Jun Lee , Woonkyung Lee
IPC分类号： H01L29/792
CPC分类号： H01L21/36 , H01L21/02521 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A semiconductor device has a substrate that includes a cell array region and a dummy pattern region surrounding the cell array region. The cell array region includes a cell structure having a plurality of cell active pillars extending in a vertical direction from the cell array region of the substrate and includes cell gate patterns and cell gate interlayer insulating patterns alternately stacked on the substrate. The cell gate patterns and cell gate interlayer insulating patterns have sides facing the cell active pillars. The dummy pattern region includes a damp-proof structure.
摘要翻译：半导体器件具有包括单元阵列区域和围绕单元阵列区域的虚设图案区域的基板。单元阵列区域包括具有从基板的单元阵列区域沿垂直方向延伸的多个单元有源柱的单元结构，并且包括交替层叠在基板上的单元栅极图案和单元栅极层间绝缘图案。单元栅极图案和单元栅极层间绝缘图案具有面向单元活性柱的侧面。虚设图案区域包括防潮结构。

27. 发明申请

US20110121403A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110121403A1
公开(公告)日：2011-05-26
申请号：US13014188
申请日：2011-01-26
申请人： Seung-Jun LEE , Woonkyung Lee
发明人： Seung-Jun LEE , Woonkyung Lee
IPC分类号： H01L27/088
CPC分类号： H01L21/36 , H01L21/02521 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A semiconductor device has a substrate that includes a cell array region and a dummy pattern region surrounding the cell array region. The cell array region includes a cell structure having a plurality of cell active pillars extending in a vertical direction from the cell array region of the substrate and includes cell gate patterns and cell gate interlayer insulating patterns alternately stacked on the substrate. The cell gate patterns and cell gate interlayer insulating patterns have sides facing the cell active pillars. The dummy pattern region includes a damp-proof structure.
摘要翻译：半导体器件具有包括单元阵列区域和围绕单元阵列区域的虚设图案区域的基板。单元阵列区域包括具有从基板的单元阵列区域沿垂直方向延伸的多个单元有源柱的单元结构，并且包括交替层叠在基板上的单元栅极图案和单元栅极层间绝缘图案。单元栅极图案和单元栅极层间绝缘图案具有面向单元活性柱的侧面。虚设图案区域包括防潮结构。

28. 发明授权

US08724394B2 Nonvolatile memory device and operating method thereof 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US08724394B2
公开(公告)日：2014-05-13
申请号：US13289463
申请日：2011-11-04
申请人： Byeong-In Choe , Changseok Kang , Woonkyung Lee
发明人： Byeong-In Choe , Changseok Kang , Woonkyung Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/10 , H01L27/1157 , H01L27/11582 , H01L29/7926
摘要： According to example embodiments, a nonvolatile memory device includes a substrate, at least one string extending vertically from the substrate, and a bit line current controlling circuit connected to the at least one string via at least one bit line. The at least one string may include a channel containing polycrystalline silicon. The bit line current controlling circuit may be configured to increase the amount of current being supplied to the bit line according to a decrease in a temperature such that a current flowing through the channel of the at least one string is increased when a temperature decreases.
摘要翻译：根据示例性实施例，非易失性存储器件包括衬底，从衬底垂直延伸的至少一个串和经由至少一个位线连接到至少一个串的位线电流控制电路。至少一个串可以包括含有多晶硅的通道。位线电流控制电路可以被配置为根据温度的降低来增加提供给位线的电流量，使得当温度降低时流过至少一个串的通道的电流增加。

29. 发明申请

US20120208347A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20120208347A1
公开(公告)日：2012-08-16
申请号：US13367792
申请日：2012-02-07
申请人： Sung-Min Hwang , Kwangmin Park , Woonkyung Lee , Jintaek Park , Byong-byun Jang , Jumi Yun
发明人： Sung-Min Hwang , Kwangmin Park , Woonkyung Lee , Jintaek Park , Byong-byun Jang , Jumi Yun
IPC分类号： H01L21/762
CPC分类号： H01L21/762 , H01L21/76224 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： Methods of fabricating a three-dimensional semiconductor device are provided. Methods may include forming a stack structure including first layers and second layers alternately stacked on a substrate, patterning the stack structure to form at least one isolation trench, forming channel structures penetrating the stack structure and being spaced apart from the isolation trench, and forming upper interconnection lines on the stack structure to connect the channel structures to each other. An isolation trench may be formed prior to formation of the channel structures.
摘要翻译：提供制造三维半导体器件的方法。方法可以包括形成堆叠结构，其包括交替层叠在衬底上的第一层和第二层，图案化堆叠结构以形成至少一个隔离沟槽，形成贯穿堆叠结构并与隔离沟槽间隔开的沟道结构，在堆叠结构上的互连线将通道结构彼此连接。可以在形成通道结构之前形成隔离沟槽。

30. 发明授权

US08729622B2 Three dimensional semiconductor memory devices and methods of fabricating the same 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US08729622B2
公开(公告)日：2014-05-20
申请号：US13276682
申请日：2011-10-19
申请人： Hui-Chang Moon , Sung-Min Hwang , Woonkyung Lee
发明人： Hui-Chang Moon , Sung-Min Hwang , Woonkyung Lee
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/11556 , H01L29/7926
摘要： A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.
摘要翻译：三维半导体存储器件具有层叠结构，其包括彼此绝缘的单元栅极和彼此横向分离的第一串选择栅极，延伸穿过第一串选择栅极的垂直有源图案，侧壁之间的多层电介质层垂直有源图案和单元栅极之间以及垂直有源图案和第一串选择栅极的侧壁之间以及至少一个第一补充导电图案。第一串选择栅极设置在单元栅极的最上面的单元栅极上。每个垂直有源图案延伸穿过堆叠在第一串选择门下的每个单元门。第一补充导电图案与第一串选择门之一的侧壁接触。

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