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21. 发明授权

US07307871B2 SRAM cell design with high resistor CMOS gate structure for soft error rate improvement 有权
标题翻译： SRAM单元设计具有高电阻CMOS栅极结构，可提高软错误率
公开(公告)号：US07307871B2
公开(公告)日：2007-12-11
申请号：US11287449
申请日：2005-11-22
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： C11C11/00 , C11C5/06 , H01L23/62 , H01L29/00 , H01L2/8238 , H01L21/44 , H01L21/4763
CPC分类号： G11C11/412
摘要： A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through a first resistor. The first memory node is coupled to an input of the second inverter through a second resistor. A pair of access transistors are respectively coupled to a pair of bit lines, a split word line and one of the memory nodes. The resistors are prepared by coating a layer of silicide material on a selective portion of the gate structure of the transistors included in the first inverter, and connecting a portion of the gate structure that is substantially void of the silicide material to the drain of the transistors included in the second inverter.
摘要翻译：降低软错误率的高电阻SRAM存储单元包括具有作为第一存储器节点的输出的第一反相器和具有作为第二存储器节点的输出的第二反相器。第二存储器节点通过第一电阻耦合到第一反相器的输入端。第一存储器节点通过第二电阻耦合到第二反相器的输入端。一对存取晶体管分别耦合到一对位线，分割字线和存储器节点之一。电阻器通过在第一反相器中包括的晶体管的栅极结构的选择性部分上涂覆一层硅化物材料并将基本上无硅化物材料的栅极结构的一部分连接到晶体管的漏极来制备包括在第二个逆变器中。

22. 发明申请

US20070018253A1 Memory cell and manufacturing methods 审中-公开
标题翻译：记忆体和制造方法
公开(公告)号：US20070018253A1
公开(公告)日：2007-01-25
申请号：US11202445
申请日：2005-08-12
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L29/76
CPC分类号： H01L27/0203 , H01L27/105 , H01L27/10873 , H01L27/10894 , H01L27/11 , H01L27/1104 , H01L27/1116
摘要： A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate, a first memory device array on the semiconductor substrate, and a logic circuit on the semiconductor substrate. Substantially all gates of at least one type of PMOS and NMOS devices in the first memory device array and the logic circuit are unidirectional. The pocket regions and lightly doped drain/source regions are therefore tilt implanted at rotation angles substantially close to 0 degrees and 180 degrees.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括半导体衬底，半导体衬底上的第一存储器件阵列和半导体衬底上的逻辑电路。第一存储器件阵列和逻辑电路中的至少一种类型的PMOS和NMOS器件的基本上所有的栅极都是单向的。因此，凹坑区域和轻掺杂的漏极/源极区域以大致接近0度和180度的旋转角度倾斜注入。

23. 发明申请

US20060131614A1 Memory cell structure 有权
标题翻译：存储单元结构
公开(公告)号：US20060131614A1
公开(公告)日：2006-06-22
申请号：US11340397
申请日：2006-01-26
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L29/768
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104 , Y10S257/903
摘要： A memory structure that reduces soft-errors for us in CMOS devices is provided. The memory cell layout utilizes transistors oriented such that the source-to-drain axis is parallel a shorted side of the memory cell. The dimensions of the memory cell are such that it has a longer side and a shorter side, wherein the longer side is preferably about twice as long as the shorter side. Such an arrangement uses a shorter well path to reduce the resistance between transistors and the well strap. The shorter well strap reduces the voltage during operation and soft errors.
摘要翻译：提供了减少CMOS器件中的软错误的存储器结构。存储单元布局利用以取向的晶体管使得源极到漏极轴平行于存储器单元的短路侧。存储单元的尺寸使得其具有较长的侧面和较短的侧面，其中较长的侧面优选为短边的两倍长。这种布置使用较短的井道以减小晶体管与井带之间的电阻。较短的井带可以降低运行过程中的电压和软错误。

24. 发明授权

US07023056B2 Memory cell structure 有权
公开(公告)号：US07023056B2
公开(公告)日：2006-04-04
申请号：US10723331
申请日：2003-11-26
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104 , Y10S257/903
摘要： A memory structure that reduces soft-errors for us in CMOS devices is provided. The memory cell layout utilizes transistors oriented such that the source-to-drain axis is parallel a shorted side of the memory cell. The dimensions of the memory cell are such that it has a longer side and a shorter side, wherein the longer side is preferably about twice as long as the shorter side. Such an arrangement uses a shorter well path to reduce the resistance between transistors and the well strap. The shorter well strap reduces the voltage during operation and soft errors.

25. 发明申请

US20050253203A1 Apparatus and method for multiple-gate semiconductor device with angled sidewalls 有权
标题翻译：具有倾斜侧壁的多栅极半导体器件的装置和方法
公开(公告)号：US20050253203A1
公开(公告)日：2005-11-17
申请号：US10844197
申请日：2004-05-12
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L21/336 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/10 , H01L29/40 , H01L29/786
CPC分类号： H01L29/7853 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/7842 , H01L29/78684
摘要： A multiple-gate transistor has an active region with a side that forms an interior angle with the base of the active region of less than 80°. A process for fabricating a FinFET includes the steps of etching a silicon-on-insulator wafer to form an active region, including the source, channel, and drain, with vertically angled sidewalls.
摘要翻译：多栅极晶体管具有有源区域，其侧面与有源区域的基极形成小于80°的内角。制造FinFET的方法包括以下步骤：蚀刻绝缘体上硅晶片以形成具有垂直成角度侧壁的源极，沟道和漏极的有源区。

26. 发明授权

US06881614B2 Shared contact for high-density memory cell design 有权
标题翻译：共享接触高密度存储单元设计
公开(公告)号：US06881614B2
公开(公告)日：2005-04-19
申请号：US10600315
申请日：2003-06-20
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L21/336 , H01L21/8244 , H01L23/48 , H01L27/11 , H01L21/81 , H01L21/366
CPC分类号： H01L27/11 , H01L27/1104
摘要： A new method and structure is created for a multi-transistor SRAM device. Standard processing steps are followed for the creation of CMOS devices of providing a patterned layer of gate material, of performing LDD impurity implants, of creating gate spacers. After the creation of the gate spacers, a new step of photoresist patterning and exposure is added. The mask for this additional step is a modified butt-contact mask, comprising enlarging the conventional butt-contact opening by between about 0.005 μm and 0.2 μm, an effect that can also be achieved by photo over-expose. This modified butt-contact mask exposes a spacer that is adjacent to the butt-contact hole, this spacer is removed. S/D impurity implant is performed after which conventional processing steps are applied for completion of the multi-transistor SRAM device.
摘要翻译：为多晶体管SRAM器件创建了一种新的方法和结构。遵循标准处理步骤，以创建提供栅极材料的图案化层，执行LDD杂质植入物的CMOS器件，产生栅极间隔物。在形成栅极间隔物之后，添加光刻胶图案化和曝光的新步骤。用于该附加步骤的掩模是改进的对接接触掩模，包括将常规对接接触开口扩大约0.005μm至0.2μm，这也可以通过曝光过度曝光实现。该修改的对接接触掩模暴露与邻接孔相邻的间隔物，该间隔物被去除。执行S / D杂质注入，之后应用传统的处理步骤来完成多晶体管SRAM器件。

27. 发明授权

US06271570B1 Trench-free buried contact 有权
标题翻译：无沟槽埋地接触
公开(公告)号：US06271570B1
公开(公告)日：2001-08-07
申请号：US09578414
申请日：2000-05-26
申请人： Kuo Ching Huang , Yean-Kuen Fang , Mong-Song Liang , Jhon-Jhy Liaw , Cheng-Ming Wu , Dun-Nian Yaung
发明人： Kuo Ching Huang , Yean-Kuen Fang , Mong-Song Liang , Jhon-Jhy Liaw , Cheng-Ming Wu , Dun-Nian Yaung
IPC分类号： H01L2976
CPC分类号： H01L29/6659 , H01L21/76895 , H01L29/66545
摘要： A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.
摘要翻译：描述了形成改进的埋地接触结的新方法。在半导体衬底的表面上设置栅极氧化硅层。沉积在栅极氧化物层上的多晶硅层。覆盖多晶硅层的硬掩模层被沉积。硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。介电材料层沉积在衬底上以填充间隙。去除了掩模层。此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。将离子注入到开口内的半导体衬底中以形成掩埋接触。选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

28. 发明授权

US06228731B1 Re-etched spacer process for a self-aligned structure 有权
标题翻译：用于自对准结构的再蚀刻间隔物工艺
公开(公告)号：US06228731B1
公开(公告)日：2001-05-08
申请号：US09374817
申请日：1999-08-16
申请人： Jhon-Jhy Liaw , Yun-Hung Shen
发明人： Jhon-Jhy Liaw , Yun-Hung Shen
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/76831 , H01L27/11
摘要： A process for forming a self-aligned contact, (SAC), structure, on an active device region in a semiconductor substrate, exposed at the bottom of a SAC opening in an insulator layer, has been developed. The process features increasing the area of the active device region, used to accommodate the overlying SAC structure, via the selective removal of the thick spacer component, of a composite spacer, located on the sides of silicon nitride capped, gate structures, performed after definition of a heavily doped source/drain region. The thick spacer component can be a polysilicon shape overlying a thin silicon oxide shape, or the thick spacer component can be a silicon oxide shape, overlying a silicon nitride shape.
摘要翻译：已经开发了在绝缘体层的SAC开口的底部露出的在半导体衬底的有源器件区域上形成自对准接触（SAC）结构的工艺。该方法的特征是通过选择性去除厚的间隔物组分，增加了用于适应上覆SAC结构的有源器件区域的面积，该复合间隔物位于在定义后执行的位于氮化硅封端的栅极结构的侧面上的复合间隔物的重掺杂源极/漏极区域。厚间隔物组分可以是覆盖薄氧化硅形状的多晶硅形状，或者厚的间隔物组分可以是覆盖氮化硅形状的氧化硅形状。

29. 发明授权

US6063711A High selectivity etching stop layer for damascene process 失效
标题翻译：用于镶嵌工艺的高选择性蚀刻停止层
公开(公告)号：US6063711A
公开(公告)日：2000-05-16
申请号：US69456
申请日：1998-04-28
申请人： Li-Chih Chao , Chia-Shiung Tsai , Chu-Yun Fu , Jhon-Jhy Liaw
发明人： Li-Chih Chao , Chia-Shiung Tsai , Chu-Yun Fu , Jhon-Jhy Liaw
IPC分类号： H01L21/768 , H01L21/304 , B24B1/00 , H01L21/461
CPC分类号： H01L21/7681 , H01L21/76807
摘要： A high selectivity etch-stop layer comprising oxynitride is disclosed for forming damascene structures in the manufacturing of semiconductor substrates. Because of its relatively high selectivity to oxides, the oxynitride etch-stop can be made thinner than the conventionally used nitride layer. Therefore, the disclosed oxynitride etch-stop layer makes it possible to avoid the cracking problems of thicker etch-stop layers as well as the associated problems of poor definition of contact or via holes in the damascene structure.
摘要翻译：公开了一种包括氮氧化物的高选择性蚀刻停止层，用于在半导体衬底的制造中形成镶嵌结构。由于氧化物的选择性相对较高，氧氮化物蚀刻停止可以比常规使用的氮化物层薄。因此，所公开的氧氮化物蚀刻停止层使得可以避免较厚的蚀刻停止层的破裂问题以及相似的在镶嵌结构中接触或通孔的定义不良的问题。

30. 发明授权

US5998249A Static random access memory design and fabrication process featuring dual self-aligned contact structures 失效
标题翻译：具有双自对准接触结构的静态随机存取存储器设计和制造工艺
公开(公告)号：US5998249A
公开(公告)日：1999-12-07
申请号：US86822
申请日：1998-05-29
申请人： Jhon-Jhy Liaw , Jin-Yuan Lee
发明人： Jhon-Jhy Liaw , Jin-Yuan Lee
IPC分类号： H01L21/8244
CPC分类号： H01L27/11 , Y10S148/02
摘要： A method for forming an SRAM cell, on a semiconductor substrate, comprised of MOSFET devices, and polysilicon load resistors, has been developed. The process for forming the SRAM cell features the use of two, self-aligned contact, (SAC), structures, a polycide SAC structure, used for contact to a source region of a MOSFET pull down transistor, and a tungsten SAC structure, used for contact to a source region of a MOSFET pass gate transistor. A buried contact region is also featured in this SRAM design and fabrication procedure, used to connect underlying active device regions, of MOSFET pull down transistors, and MOSFET pass gate transistors.
摘要翻译：已经开发了用于形成由MOSFET器件和多晶硅负载电阻器构成的半导体衬底上的SRAM单元的方法。用于形成SRAM单元的工艺特征在于使用两个自对准接触（SAC），结构，用于与MOSFET下拉晶体管的源极区域接触的多晶硅SAC结构，以及钨SAC结构用于与MOSFET栅极晶体管的源极区域接触。这种SRAM设计和制造过程中还涉及一个埋置接触区域，用于连接底层有源器件区域，MOSFET下拉晶体管和MOSFET栅极晶体管。

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