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21. 发明授权

US07920621B2 Digital adaptation circuitry and methods for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的数字适配电路和方法
公开(公告)号：US07920621B2
公开(公告)日：2011-04-05
申请号：US11522284
申请日：2006-09-14
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

22. 发明授权

US07659745B1 Variable external interface circuitry on programmable logic device integrated circuits 失效
标题翻译：可编程逻辑器件集成电路上的可变外部接口电路
公开(公告)号：US07659745B1
公开(公告)日：2010-02-09
申请号：US12218688
申请日：2008-07-16
申请人： Wilson Wong , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
发明人： Wilson Wong , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H03K19/0175 , H03K5/00 , G06F7/38
CPC分类号： H03K19/17744
摘要： A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.
摘要翻译：可编程逻辑器件（“PLD”）包括用于在几个方面中的任何一个中可选地且可变地修改输入信号的特性的电路。这样的修改的示例包括将信号AC耦合到PLD中，对信号进行低通滤波（具有可选择的低通滤波器转角频率），移位输入信号的公共电压，和/或使输入信号经受可选择量的衰减。

23. 发明授权

US07417462B1 Variable external interface circuitry on programmable logic device integrated circuits 失效
标题翻译：可编程逻辑器件集成电路上的可变外部接口电路
公开(公告)号：US07417462B1
公开(公告)日：2008-08-26
申请号：US11726174
申请日：2007-03-20
申请人： Wilson Wong , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
发明人： Wilson Wong , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H03K19/0175 , H03K5/00 , G06F7/38
CPC分类号： H03K19/17744
摘要： A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.
摘要翻译：可编程逻辑器件（“PLD”）包括用于在几个方面中的任何一个中可选地且可变地修改输入信号的特性的电路。这样的修改的示例包括将信号AC耦合到PLD中，对信号进行低通滤波（具有可选择的低通滤波器转角频率），移位输入信号的公共电压，和/或使输入信号经受可选择量的衰减。

24. 发明授权

US07791370B1 Clock distribution techniques for channels 有权
标题翻译：频道的时钟分配技术
公开(公告)号：US07791370B1
公开(公告)日：2010-09-07
申请号：US12470455
申请日：2009-05-21
申请人： Tim Tri Hoang , Thungoc M. Tran , Wilson Wong , Sergey Shumarayev
发明人： Tim Tri Hoang , Thungoc M. Tran , Wilson Wong , Sergey Shumarayev
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G06F1/10
摘要： A circuit includes a first area, a second area, and a third area. The second area includes a locked loop circuit that generates a clock signal. The locked loop circuit receives a supply voltage that is isolated from noise generated in the first area. The third area includes multiple quads of channels and a clock line coupled to route at least one clock signal generated in the second area to the channels in each of the quads. The third area is separate from the second area in the circuit.
摘要翻译：电路包括第一区域，第二区域和第三区域。第二区域包括产生时钟信号的锁定环路电路。锁定环电路接收与第一区域中产生的噪声隔离的电源电压。第三区域包括多个通道的四通道，并且时钟线耦合以将在第二区域中产生的至少一个时钟信号路由到每个四通道中的通道。第三个区域与电路中的第二个区域分开。

25. 发明申请

US20080258765A1 Low-power transceiver architectures for programmable logic integrated circuit devices 有权
标题翻译：用于可编程逻辑集成电路器件的低功耗收发器架构
公开(公告)号：US20080258765A1
公开(公告)日：2008-10-23
申请号：US12214466
申请日：2008-06-18
申请人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Richard G. Cliff
发明人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Richard G. Cliff
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17744 , H03K19/17784
摘要： High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.
摘要翻译：可编程逻辑器件集成电路（“PLD”）上的高速串行接口或收发器电路包括允许PLD满足广泛可能的用户需求或应用的功能。该范围包括高性能应用和PLD降低功耗很重要的应用。在后一种情况下，可以使用各种特征中的任何一种或多种来帮助降低功耗。

26. 发明授权

US07414429B1 Integration of high-speed serial interface circuitry into programmable logic device architectures 有权
标题翻译：将高速串行接口电路集成到可编程逻辑器件架构中
公开(公告)号：US07414429B1
公开(公告)日：2008-08-19
申请号：US11486867
申请日：2006-07-14
申请人： In Whan Kim , Sergey Shumarayev , Tim Tri Hoang , Wilson Wong , Thungoc M. Tran
发明人： In Whan Kim , Sergey Shumarayev , Tim Tri Hoang , Wilson Wong , Thungoc M. Tran
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H03K19/0175 , H01L25/00
CPC分类号： H03K19/17744
摘要： The architecture of a programmable logic device (“PLD”) is modified in one or more of several respects to facilitate inclusion of high-speed serial interface (“HSSI”) circuitry in the PLD. For example, the HSSI circuitry is preferably located along one side of the device, taking the place of regular peripheral IO circuitry in that area. Certain portions of the core logic circuitry are modified to better interface with the HSSI circuitry.
摘要翻译：可编程逻辑器件（“PLD”）的架构在几个方面中的一个或多个方面进行了修改，以便于在PLD中包含高速串行接口（“HSSI”）电路。例如，HSSI电路优选地位于设备的一侧，代替该区域中的常规外设IO电路。核心逻辑电路的某些部分被修改以更好地与HSSI电路接口。

27. 发明申请

US20080069276A1 Digital adaptation circuitry and methods for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的数字适配电路和方法
公开(公告)号：US20080069276A1
公开(公告)日：2008-03-20
申请号：US11522284
申请日：2006-09-14
申请人： Wilson Wong , Doris Po Ching Chan , Simardeep Maangat , Sergey Shumarayev , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Simardeep Maangat , Sergey Shumarayev , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H04B1/10
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

28. 发明授权

US08416001B2 Techniques for reducing duty cycle distortion in periodic signals 有权
标题翻译：降低周期信号中占空比失真的技术
公开(公告)号：US08416001B2
公开(公告)日：2013-04-09
申请号：US13083431
申请日：2011-04-08
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03K5/1565 , H03K3/017 , H03K5/12 , H03M9/00
摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.
摘要翻译：发射机电路可操作以响应于第一周期性信号提供输出信号。多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。采样器电路可操作以在第一操作阶段产生所选信号的第一采样。采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

29. 发明申请

US20120256670A1 Techniques for Reducing Duty Cycle Distortion in Periodic Signals 有权
标题翻译：降低周期信号占空比变形的技术
公开(公告)号：US20120256670A1
公开(公告)日：2012-10-11
申请号：US13083431
申请日：2011-04-08
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K3/017 , H03K5/12 , H03M9/00
摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.
摘要翻译：发射机电路可操作以响应于第一周期性信号提供输出信号。多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。采样器电路可操作以在第一操作阶段产生所选信号的第一采样。采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

30. 发明授权

US08081723B1 Serial data signal eye width estimator methods and apparatus 有权
标题翻译：串行数据信号眼宽估计方法和装置
公开(公告)号：US08081723B1
公开(公告)日：2011-12-20
申请号：US12082343
申请日：2008-04-09
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran
IPC分类号： H04L7/00
CPC分类号： H04L7/048 , H04L1/205 , H04L7/033
摘要： Methods and apparatus for determining at least part of the width of the eye of a high-speed serial data signal use clock and data recovery circuitry operating on that signal to produce a first clock signal having a first phase relationship to the data signal. The first clock signal is used to produce a second clock signal whose phase can be controllably shifted relative to the first phase. The second clock signal is used to sample the data signal with different amounts of phase shift, e.g., until error checking circuitry detects that data errors in the resulting sample exceed an acceptable threshold for such errors. The amount(s) of phase shift that caused exceeding the threshold can be used as a basis for a measurement of eye width.
摘要翻译：用于确定高速串行数据信号的眼睛的至少部分宽度的方法和装置使用在该信号上操作的时钟和数据恢复电路，以产生与数据信号具有第一相位关系的第一时钟信号。第一时钟信号用于产生第二时钟信号，其相位可相对于第一相位被可控地偏移。第二时钟信号用于以不同量的相移对数据信号进行采样，例如直到错误检查电路检测到所得样本中的数据错误超过这种错误的可接受的阈值。引起超过阈值的相移量可用作测量眼睛宽度的基础。

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