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21. 发明授权

US08080440B2 Resistor random access memory cell with L-shaped electrode 有权
标题翻译：具有L形电极的电阻随机存取存储单元
公开(公告)号：US08080440B2
公开(公告)日：2011-12-20
申请号：US12769466
申请日：2010-04-28
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： H01L21/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A phase change random access memory PCRAM device is described suitable for use in large-scale integrated circuits. An exemplary memory device has a pipe-shaped first electrode formed from a first electrode layer on a sidewall of a sidewall support structure. A sidewall spacer insulating member is formed from a first oxide layer and a second, “L-shaped,” electrode is formed on the insulating member. An electrical contact is connected to the horizontal portion of the second electrode. A bridge of memory material extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall spacer insulating member.
摘要翻译：描述适用于大规模集成电路的相变随机存取存储器PCRAM器件。示例性存储器件具有由侧壁支撑结构的侧壁上的第一电极层形成的管状第一电极。侧壁间隔绝缘部件由第一氧化物层形成，第二“L”形电极形成在绝缘部件上。电触头连接到第二电极的水平部分。记忆材料桥从第一电极的顶表面延伸到第二电极的顶表面，跨过侧壁间隔绝缘件的顶表面。

22. 发明授权

US08022466B2 Non-volatile memory cells having a polysilicon-containing, multi-layer insulating structure, memory arrays including the same and methods of operating the same 有权
标题翻译：具有含多晶硅的多层绝缘结构的非易失性存储单元，包括其的存储器阵列及其操作方法
公开(公告)号：US08022466B2
公开(公告)日：2011-09-20
申请号：US11588830
申请日：2006-10-27
申请人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , G11C16/0466 , H01L29/513 , H01L29/66833 , H01L29/792
摘要： Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material layer interposed between a first dielectric layer and a second dielectric layer; and a gate disposed above the upper insulating multi-layer structure are described along with arrays thereof and methods of operation.
摘要翻译：存储单元包括具有至少两个源极/漏极区域的半导体层，所述源极/漏极区域设置在半导体层的表面下方并被沟道区域分隔开; 设置在通道区域上方的下绝缘层; 电荷存储层，其设置在所述下绝缘层的上方; 上部绝缘多层结构，其设置在所述电荷存储层上方，其中所述上部绝缘多层结构包括介于第一介电层和第二介电层之间的多晶硅材料层; 并且设置在上绝缘多层结构上方的栅极及其阵列及其操作方法。

23. 发明授权

US07697316B2 Multi-level cell resistance random access memory with metal oxides 有权
标题翻译：具有金属氧化物的多层电池随机存取存储器
公开(公告)号：US07697316B2
公开(公告)日：2010-04-13
申请号：US11567978
申请日：2006-12-07
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： G11C11/00
CPC分类号： G11C13/0016 , G11C11/5664 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/0014 , H01L45/04 , H01L45/124 , H01L45/146 , H01L45/1633
摘要： A bistable resistance random access memory comprises a plurality of programmable resistance random access memory cells where each programmable resistance random access memory cell includes multiple memory members for performing multiple bits for each memory cell. The bistable RRAM includes a first resistance random access member connected to a second resistance random access member through interconnect metal liners and metal oxide strips. The first resistance random access member has a first resistance value Ra, which is determined from the thickness of the first resistance random access member based on the deposition of the first resistance random access member. The second resistance random access member has a second resistance value Rb, which is determined from the thickness of the second resistance random access member based on the deposition of the second resistance random access member.
摘要翻译：双稳态电阻随机存取存储器包括多个可编程电阻随机存取存储单元，其中每个可编程电阻随机存取存储单元包括用于为每个存储单元执行多位的多个存储器构件。双稳态RRAM包括通过互连金属衬垫和金属氧化物条连接到第二电阻随机存取构件的第一电阻随机存取构件。第一电阻随机存取构件具有基于第一电阻随机存取构件的沉积从第一电阻随机存取构件的厚度确定的第一电阻值Ra。第二电阻随机存取部件具有基于第二电阻随机存取部件的沉积从第二电阻随机存取部件的厚度确定的第二电阻值Rb。

24. 发明申请

US20100039846A1 Method and Apparatus for Non-Volatile Multi-Bit Memory 有权
标题翻译：非易失性多位存储器的方法和装置
公开(公告)号：US20100039846A1
公开(公告)日：2010-02-18
申请号：US12576212
申请日：2009-10-08
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： G11C5/02 , G11C11/00
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C2213/31 , G11C2213/32 , G11C2213/34 , G11C2213/79 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/122 , H01L45/144 , H01L45/146 , H01L45/1633
摘要： A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-sectional area less than that of the second memory layer.
摘要翻译：可选择地显示第一和第二逻辑电平的存储器件。第一导电材料具有形成在其上的第一存储层的第一表面，并且第二导电材料具有形成在其上的第二存储层的第二表面。连接导电层连接第一和第二存储层并将其放置在电接触中。该结构被设计成使得第一存储层的横截面积小于第二存储层的横截面面积。

25. 发明授权

US07608848B2 Bridge resistance random access memory device with a singular contact structure 有权
标题翻译：具有单一接触结构的桥接电阻随机存取存储器件
公开(公告)号：US07608848B2
公开(公告)日：2009-10-27
申请号：US11382422
申请日：2006-05-09
申请人： ChiaHua Ho , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： ChiaHua Ho , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L29/04
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A resistance random access memory in a bridge structure is disclosed that comprises a contact structure where first and second electrodes are located within the contact structure. The first electrode has a circumferential extending shape, such as an annular shape, surrounding an inner wall of the contact structure. The second electrode is located within an interior of the circumferential extending shape and separated from the first electrode by an insulating material. A resistance memory bridge is in contact with an edge surface of the first and second electrodes. The first electrode in the contact structure is connected to a transistor and the second electrode in the contact structure is connected to a bit line. A bit line is connected to the second electrode by a self-aligning process.
摘要翻译：公开了一种桥结构中的电阻随机存取存储器，其包括其中第一和第二电极位于接触结构内的接触结构。第一电极具有围绕接触结构的内壁的周向延伸形状，例如环形形状。第二电极位于周向延伸形状的内部，并通过绝缘材料与第一电极分离。电阻记忆桥与第一和第二电极的边缘表面接触。接触结构中的第一电极连接到晶体管，并且接触结构中的第二电极连接到位线。位线通过自对准工艺连接到第二电极。

26. 发明申请

US20090236743A1 Programmable Resistive RAM and Manufacturing Method 有权
标题翻译：可编程电阻RAM和制造方法
公开(公告)号：US20090236743A1
公开(公告)日：2009-09-24
申请号：US12477811
申请日：2009-06-03
申请人： Chiahua Ho , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L23/498
CPC分类号： H01L27/24 , H01L28/26
摘要： Programmable resistive RAM cells have a resistance that depends on the size of the contacts. Manufacturing methods and integrated circuits for lowered contact resistance are disclosed that have contacts of reduced size.
摘要翻译：可编程电阻RAM单元具有取决于触点尺寸的电阻。公开了具有降低的接触电阻的制造方法和集成电路，其具有减小的尺寸的接触。

27. 发明授权

US07554144B2 Memory device and manufacturing method 有权
标题翻译：存储器件及制造方法
公开(公告)号：US07554144B2
公开(公告)日：2009-06-30
申请号：US11279945
申请日：2006-04-17
申请人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
IPC分类号： H01L29/417
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1253 , H01L45/14 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A memory device includes first and second electrodes separated by an insulating member comprising upwardly and inwardly tapering surfaces connected by a surface segment. A bridge, comprising memory material, such as a phase change material, switchable between electrical property states by the application of energy, is positioned across the surface segment and in contact with the electrodes to define an inter-electrode path defined at least in part by the length of the surface segment. According to a method for making a memory cell device, the tapering surfaces may be created by depositing a dielectric material cap using a high density plasma (HDP) deposition procedure. The electrodes and the dielectric material cap may he planarized to create the surface segment on the dielectric material. At least one of the dielectric material depositing step and the planarizing step may be controlled so that the length of the surface and segment is within a chosen dimensional range, such as between 10 nm and 100 nm.
摘要翻译：存储器件包括由绝缘构件隔开的第一和第二电极，包括由表面段连接的向上和向内的渐缩表面。包括可通过施加能量在电性能状态之间切换的记忆材料（例如相变材料）的桥被定位在表面段上并与电极接触以限定至少部分地由表面段的长度。根据制造存储单元器件的方法，可以通过使用高密度等离子体（HDP）沉积程序沉积介电材料盖而产生锥形表面。电极和电介质材料盖可以被平坦化以在电介质材料上产生表面段。可以控制介电材料沉积步骤和平坦化步骤中的至少一个，使得表面和段的长度在选定的尺寸范围内，例如在10nm和100nm之间。

28. 发明申请

US20090072211A1 Resistive random access memory and method for manufacturing the same 有权
标题翻译：电阻随机存取存储器及其制造方法
公开(公告)号：US20090072211A1
公开(公告)日：2009-03-19
申请号：US11898529
申请日：2007-09-13
申请人： Ming-Daou Lee , Chia-Hua Ho , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Ming-Daou Lee , Chia-Hua Ho , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/1633
摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.
摘要翻译：提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。绝缘层设置在底部电极上。绝缘层具有第一宽度的接触孔。硬掩模层具有开口。存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。顶部电极设置在绝缘层上并与存储单元耦合。

29. 发明申请

US20090032793A1 Resistor Random Access Memory Structure Having a Defined Small Area of Electrical Contact 有权
标题翻译：电阻随机存取存储器结构具有定义的小面积的电触点
公开(公告)号：US20090032793A1
公开(公告)日：2009-02-05
申请号：US11833563
申请日：2007-08-03
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144
摘要： A memory cell device, of the type that includes a memory material switchable between electrical property states by application of energy, includes first and second electrodes, a plug of memory material (such as phase change material) which is in electrical contact with the second electrode, and an electrically conductive film which is supported by a dielectric form and which is in electrical contact with the first electrode and with the memory material plug. The dielectric form is wider near the first electrode, and is narrower near the phase change plug. The area of contact of the conductive film with the phase change plug is defined in part by the geometry of the dielectric form over which the conductive film is formed. Also, methods for making the device include steps of constructing a dielectric form over a first electrode, and forming a conductive film over the dielectric form.
摘要翻译：包括能够通过施加能量在电性能状态之间切换的存储材料的存储单元装置包括第一和第二电极，与第二电极电接触的存储材料（例如相变材料）插头以及由电介质形式支撑并与第一电极和记忆材料塞电接触的导电膜。电介质形式在第一电极附近较宽，在相变插头附近较窄。导电膜与相变插塞的接触面积部分地由形成导电膜的电介质形状的几何形状限定。此外，制造该器件的方法包括在第一电极上构建电介质形式，以及在电介质形式上形成导电膜的步骤。

30. 发明授权

US07450423B2 Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure 有权
公开(公告)号：US07450423B2
公开(公告)日：2008-11-11
申请号：US11649348
申请日：2007-01-03
申请人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
IPC分类号： G11C11/34 , G11C16/06 , H01L29/94
CPC分类号： H01L29/792 , G11C16/0466 , G11C16/0475 , G11C16/14 , H01L21/28282 , H01L29/4234 , H01L29/513
摘要： A method of operating a memory cell by applying a positive voltage to the gate sufficient to cause hole tunneling from the gate toward the charge storage layer is disclosed. The method is applied to a memory cell including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region. The memory cell also has a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer. The upper insulating multi-layer structure comprises a lower dielectric layer and an upper nitride layer disposed above the lower dielectric layer and the memory cell has a gate disposed above the upper insulating multi-layer structure.

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