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21. 发明申请

US20050032328A1 Chemical mechanical polishing in forming semiconductor device 有权
标题翻译：化学机械抛光成型半导体器件
公开(公告)号：US20050032328A1
公开(公告)日：2005-02-10
申请号：US10939716
申请日：2004-09-13
申请人： Ming-Sheng Yang , Juan-Yuan Wu , Water Lur
发明人： Ming-Sheng Yang , Juan-Yuan Wu , Water Lur
IPC分类号： H01L21/762 , H01L21/00 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76229
摘要： A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.
摘要翻译：公开了用于形成浅沟槽隔离的化学机械抛光的方法。提供了具有多个有效区域的基板，包括多个相对较大的有源区域和多个相对小的有源区域。该方法包括以下步骤。形成衬底上的氮化硅层。在有源区域之间形成多个浅沟槽，其中一个或多个可以构成对准标记。在衬底上形成氧化物层，使得浅沟槽被氧化物层填充。在氧化物层上形成部分反向有源掩模。部分反向有源掩模将氧化物层的一部分暴露在大的有效区域上方和对准标记之上。去除每个大活性区域的氧化物层和对准标记。去除部分反向主动掩模。氧化层平坦化。

22. 发明授权

US5422312A Method for forming metal via 失效
标题翻译：金属通孔形成方法
公开(公告)号：US5422312A
公开(公告)日：1995-06-06
申请号：US254122
申请日：1994-06-06
申请人： David Lee , Water Lur
发明人： David Lee , Water Lur
IPC分类号： H01L21/311 , H01L21/768 , H01L21/28 , H01L21/31
CPC分类号： H01L21/76802 , H01L21/31144 , Y10S148/105
摘要： A method of forming a metal via on a semiconductor substrate having a metal layer and a dielectric layer on the metal layer, which uses an intermediate mask layer as a mask in forming the metal via instead of using a photoresist as a mask. Therefore, the spin-on glass (SOG) layer in the dielectric layer is not exposed to plasma or solvent, thereby preventing the formation of polymers which cause poor step coverage and sometimes even contact failure in the metal via.
摘要翻译：在金属层上具有金属层和电介质层的半导体衬底上形成金属通孔的方法，其中使用中间掩模层作为掩模来形成金属通孔，而不是使用光致抗蚀剂作为掩模。因此，电介质层中的旋涂玻璃（SOG）层不暴露于等离子体或溶剂中，从而防止在金属通孔中导致差的阶梯覆盖和有时甚至接触故障的聚合物的形成。

23. 发明授权

US08062536B2 High density plasma chemical vapor deposition process 有权
标题翻译：高密度等离子体化学气相沉积工艺
公开(公告)号：US08062536B2
公开(公告)日：2011-11-22
申请号：US12729234
申请日：2010-03-22
申请人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/467 , H01L21/32 , H01L21/308 , H01L21/762
CPC分类号： H01L21/02112 , H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/31612 , H01L21/32136 , H01L21/32139 , H01L21/76834 , H01L21/76837 , H01L21/76838
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
摘要翻译：在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括形成盖层并形成间隙，沉积高密度等离子体化学气相沉积（HDPCVD）电介质材料。第一和第二抗反射涂层可以形成在布线层上，第一和第二抗反射涂层由不同的材料制成。防反射涂层和布线层都被蚀刻通过以形成由间隙分开的布线。可以使用高密度等离子体化学气相沉积来填充布线之间的间隙。

24. 发明授权

US07378740B2 Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit 有权
标题翻译：用于集成电路中多级互连的布线结构的双镶嵌结构
公开(公告)号：US07378740B2
公开(公告)日：2008-05-27
申请号：US11196038
申请日：2005-08-02
申请人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7681 , H01L21/76832 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.
摘要翻译：提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

25. 发明申请

US20060099824A1 High density plasma chemical vapor deposition process 有权
公开(公告)号：US20060099824A1
公开(公告)日：2006-05-11
申请号：US11315904
申请日：2005-12-22
申请人： Chih-Chien Liu , Ta-Shan Tseng , W.B. Shieh , J.Y. Wu , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , Ta-Shan Tseng , W.B. Shieh , J.Y. Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/31
CPC分类号： H01L21/02112 , H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/31612 , H01L21/32136 , H01L21/32139 , H01L21/76834 , H01L21/76837 , H01L21/76838
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

26. 发明申请

US20060009005A1 CHEMICAL MECHANICAL POLISHING FOR FORMING A SHALLOW TRENCH ISOLATION STRUCTURE 有权
标题翻译：用于形成浅层隔离结构的化学机械抛光
公开(公告)号：US20060009005A1
公开(公告)日：2006-01-12
申请号：US10984045
申请日：2004-11-09
申请人： Coming Chen , Juan-Yuan Wu , Water Lur
发明人： Coming Chen , Juan-Yuan Wu , Water Lur
IPC分类号： H01L21/76 , H01L21/302
CPC分类号： H01L21/31144 , H01L21/31053 , H01L21/31056 , H01L21/76229 , Y10S438/942
摘要： A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relatively large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.
摘要翻译：公开了用于形成浅沟槽隔离的化学机械抛光的方法。提供具有多个有源区的基板，包括多个相对较大的有源区和多个相对小的有源区。该方法包括以下步骤。首先形成衬底上的氮化硅层。在活性区域之间形成多个浅沟槽。在衬底上形成氧化物层，使得浅沟槽被氧化物层填充。在氧化物层上形成部分反向有源掩模。部分反向有源掩模在每个相对大的有效区域的中心部分具有开口。开口暴露氧化物层的一部分。开口至少有一个虚拟图案。去除每个大的有源区的中心部分的氧化物层，以露出氮化硅层。去除部分反向主动掩模。将氧化物层平坦化以暴露氮化硅层。

27. 发明授权

US06810511B2 Method of designing active region pattern with shift dummy pattern 有权
标题翻译：用移动虚拟图案设计有源区域图案的方法
公开(公告)号：US06810511B2
公开(公告)日：2004-10-26
申请号：US10284683
申请日：2002-10-30
申请人： Coming Chen , Juan-Yuan Wu , Water Lur
发明人： Coming Chen , Juan-Yuan Wu , Water Lur
IPC分类号： G06F1750
CPC分类号： H01L21/31053 , H01L21/76229 , H01L23/528 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.
摘要翻译：一种设计具有偏移的虚设图案的有源区域图案的方法，其中提供其上具有原始有源区域图案的集成电路。原始活动区域图案用线宽的第一参数展开以获得第一图案。通过减去第一图案，获得第二图案。提供了包括多个元件的阵列的虚拟图案。通过移动元件，获得移动的虚拟图案。第二图案和移位的虚拟图案被组合，使得其重叠区域被提取为组合的虚拟图案。组合的虚拟图案用线宽的第二参数扩展，从而获得合成的虚拟图案。将所得到的虚拟图案添加到第一图案，从而获得具有偏移的虚设图案的有源区域图案。

28. 发明授权

US6159845A Method for manufacturing dielectric layer 有权
标题翻译：电介质层制造方法
公开(公告)号：US6159845A
公开(公告)日：2000-12-12
申请号：US395906
申请日：1999-09-11
申请人： Tri-Rung Yew , Water Lur , Hsien-Ta Chung
发明人： Tri-Rung Yew , Water Lur , Hsien-Ta Chung
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/7681 , H01L21/7682 , H01L21/7684 , H01L21/76885
摘要： A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.
摘要翻译：描述双镶嵌互连中的电介质层。在基板上形成双镶嵌互连结构。所述双镶嵌互连结构具有形成在所述基板上的第一电介质层，形成在所述第一电介质层上的第二电介质层，穿过所述第二电介质层的第一电线和第二导线。第二线穿透第二电介质层并且电耦合到衬底。去除第二介电层。保护层形成在衬底上。第三电介质层形成在阻挡盖层上，并且在由第三电介质层，第一和第二电线围绕的空间中形成气隙。在第三电介质层上形成第四电介质层。执行平面化处理以平坦化第四介电层。

29. 发明授权

US6100205A Intermetal dielectric layer formation with low dielectric constant using high density plasma chemical vapor deposition process 失效
标题翻译：使用高密度等离子体化学气相沉积工艺，具有低介电常数的金属间介电层形成
公开(公告)号：US6100205A
公开(公告)日：2000-08-08
申请号：US958828
申请日：1997-10-28
申请人： Chih-Chien Liu , J. Y. Wu , Tsang-Jung Lin , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , J. Y. Wu , Tsang-Jung Lin , Water Lur , Shih-Wei Sun
IPC分类号： C23C16/04 , C23C16/40 , C23C16/50 , H01L21/316 , H01L21/768 , H01L21/31
CPC分类号： H01L21/02164 , C23C16/045 , C23C16/402 , C23C16/50 , H01L21/022 , H01L21/02274 , H01L21/02304 , H01L21/31612 , H01L21/76801
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of dielectric layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out to form a first dielectric layer over the wiring lines and into the gaps between wiring lines. A PECVD step is carried out to deposit dielectric material over the first dielectric layer and within and to define a opening in the gap. A second HDPCVD step is carried out and the opening defined by the PECVD step is capped by a third dielectric layer. The method allows air-filled voids to be formed between adjacent metal wiring lines in a highly controlled manner which allows selection of the shape of the voids and precise location of the top of the voids. In addition, the voids are sealed by a denser and more durable material than is typical.
摘要翻译：在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括使用高密度等离子体化学气相沉积（HDPCVD）沉积介电层。执行第一HDPCVD步骤以在布线上形成布线之间的间隙中的第一介电层。执行PECVD步骤以将电介质材料沉积在第一介电层上并且在间隙内并限定开口。执行第二HDPCVD步骤，并且由PECVD步骤限定的开口被第三介电层覆盖。该方法允许以相当可控的方式在相邻的金属布线之间形成空气填充的空隙，这允许选择空隙的形状和空隙的顶部的精确定位。此外，空隙通过比典型的更致密和更耐用的材料密封。

30. 发明授权

US6087262A Method for manufacturing shallow trench isolation structure 有权
标题翻译：浅沟槽隔离结构的制造方法
公开(公告)号：US6087262A
公开(公告)日：2000-07-11
申请号：US189140
申请日：1998-11-09
申请人： Gwo-Shii Yang , Kuo-Tai Huang , Tri-Rung Yew , Water Lur
发明人： Gwo-Shii Yang , Kuo-Tai Huang , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/00
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method for manufacturing shallow trench isolation structure includes the steps of fabricating a self-aligned silicon nitride mask over the trench region so that a kink effect due to the misalignment of mask during a conventional mask-making process can be avoided. Moreover, the silicon nitride mask requires fewer steps and less complicated operations to construct than a conventional reverse tone mask.
摘要翻译：用于制造浅沟槽隔离结构的方法包括以下步骤：在沟槽区域上制造自对准氮化硅掩模，从而可以避免在常规掩模制造工艺期间由于掩模的未对准而产生的扭结效应。此外，与传统的反向色调掩模相比，氮化硅掩模需要更少的步骤和更少的复杂操作来构造。

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