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21. 发明申请

US20070099353A1 Method for forming a semiconductor structure and structure thereof 有权
标题翻译：半导体结构的形成方法及其结构
公开(公告)号：US20070099353A1
公开(公告)日：2007-05-03
申请号：US11263120
申请日：2005-10-31
申请人： Voon-Yew Thean , Jian Chen , Bich-Yen Nguyen , Mariam Sadaka , Da Zhang
发明人： Voon-Yew Thean , Jian Chen , Bich-Yen Nguyen , Mariam Sadaka , Da Zhang
IPC分类号： H01L21/84
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/7842 , H01L29/785 , Y10S438/938
摘要： Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.
摘要翻译：形成半导体结构包括提供具有覆盖在绝缘层上的应变半导体层的衬底，提供用于形成具有第一导电类型的第一多个器件的第一器件区域，提供第二器件区域，用于形成具有第第二导电类型，并且使第二器件区域中的应变半导体层变厚，使得第二器件区域中的应变半导体层具有较小的第一器件区域中的应变半导体层的应变。或者，形成半导体结构包括提供具有第一导电类型的第一区域，形成覆盖第一区域的至少有源区域的绝缘层，各向异性地蚀刻绝缘层，以及在各向异性蚀刻绝缘层之后，覆盖绝缘层的至少一部分的材料。

22. 发明申请

US20070218707A1 Electronic device including semiconductor islands of different thicknesses over an insulating layer and a process of forming the same 有权
标题翻译：包括在绝缘层上具有不同厚度的半导体岛的电子器件及其形成方法
公开(公告)号：US20070218707A1
公开(公告)日：2007-09-20
申请号：US11375893
申请日：2006-03-15
申请人： Mariam Sadaka , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Mariam Sadaka , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/31
CPC分类号： H01L21/32 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/84
摘要： A process of forming an electronic device can include forming a patterned oxidation-resistant layer over a semiconductor layer that overlies a substrate, and patterning the semiconductor layer to form a semiconductor island. The semiconductor island includes a first surface and a second surface opposite the first surface, and the first surface lies closer to the substrate, as compared to the second surface. The process can also include forming an oxidation-resistant material along a side of the semiconductor island or selectively depositing a semiconductor material along a side of the semiconductor island. The process can further include exposing the patterned oxidation-resistant layer and the semiconductor island to an oxygen-containing ambient, wherein a first portion of the semiconductor island along the first surface is oxidized during exposing the patterned oxidation-resistant layer, the semiconductor island, and the oxidation-resistant material to an oxygen-containing ambient.
摘要翻译：形成电子器件的方法可以包括在覆盖在衬底上的半导体层上形成图案化的抗氧化层，并且图案化半导体层以形成半导体岛。半导体岛包括与第一表面相对的第一表面和第二表面，并且第一表面与第二表面相比更靠近基底。该方法还可以包括沿着半导体岛的一侧形成耐氧化材料或者沿半导体岛的一侧选择性地沉积半导体材料。该方法还可以包括将图案化的抗氧化层和半导体岛暴露于含氧环境中，其中沿着第一表面的半导体岛的第一部分在曝光图案化的抗氧化层，半导体岛，并将抗氧化材料转化为含氧环境。

23. 发明申请

US20070210381A1 Electronic device and a process for forming the electronic device 有权
标题翻译：电子设备和用于形成电子设备的过程
公开(公告)号：US20070210381A1
公开(公告)日：2007-09-13
申请号：US11374372
申请日：2006-03-13
申请人： Mariam Sadaka , Venkat Kolagunta , William Taylor , Victor Vartanian
发明人： Mariam Sadaka , Venkat Kolagunta , William Taylor , Victor Vartanian
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/76256 , H01L27/1203 , H01L29/7842 , H01L29/785 , H01L29/78687
摘要： An electronic device can have an insulating layer lying between a first semiconductor layer and a base layer. A second semiconductor layer, having a different composition and stress as compared to the first semiconductor layer, can overlie at least a portion of the first semiconductor layer. In one embodiment, a first electronic component can include a first active region that includes a first portion of the first and the second semiconductor layers. A second electronic component can include a second active region that can include a second portion of the first semiconductor layer. Different processes can be used to form the electronic device. In another embodiment, annealing a workpiece can be performed and the stress of at least one of the semiconductor layers can be changed. In a different embodiment, annealing the workpiece can be performed either before or after the formation of the second semiconductor layer.
摘要翻译：电子设备可以具有位于第一半导体层和基底层之间的绝缘层。与第一半导体层相比具有不同组成和应力的第二半导体层可以覆盖在第一半导体层的至少一部分上。在一个实施例中，第一电子部件可以包括第一有源区，其包括第一和第二半导体层的第一部分。第二电子部件可以包括可以包括第一半导体层的第二部分的第二有源区。可以使用不同的过程来形成电子设备。在另一个实施例中，可以执行退火工件，并且可以改变至少一个半导体层的应力。在不同的实施例中，退火工件可以在第二半导体层的形成之前或之后进行。

24. 发明申请

US20070238233A1 Method of making a multiple crystal orientation semiconductor device 有权
标题翻译：制造多晶体取向半导体器件的方法
公开(公告)号：US20070238233A1
公开(公告)日：2007-10-11
申请号：US11393563
申请日：2006-03-30
申请人： Mariam Sadaka , Bich-Yen Nguyen , Ted White
发明人： Mariam Sadaka , Bich-Yen Nguyen , Ted White
IPC分类号： H01L21/337
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207
摘要： A method of having transistors formed in enhanced performance crystal orientations begins with a wafer having a semiconductor substrate (12,52) of a first surface orientation, a thin etch stop layer (14,54) on the semiconductor substrate, a buried oxide layer (16,56) on the thin etch stop layer, and a semiconductor layer (18,58) of a second surface orientation on the buried oxide layer. An etch penetrates to the thin etch stop layer. Another etch, which is chosen to minimize the damage to the underlying semiconductor substrate, exposes a portion of the semiconductor substrate. An epitaxial semiconductor (28,66) is then grown from the exposed portion of the semiconductor substrate to form a semiconductor region having the first surface orientation and having few, if any, defects. The epitaxially grown semiconductor region is then used for enhancing one type of transistor while the semiconductor layer of the second surface orientation is used for enhancing a different type of transistor.
摘要翻译：以增强的性能晶体取向形成的晶体管的方法从具有第一表面取向的半导体衬底（12,52），半导体衬底上的薄蚀刻停止层（14,54），掩埋氧化物层（ 16,56）和在所述掩埋氧化物层上的第二表面取向的半导体层（18,58）。蚀刻渗透到薄的蚀刻停止层。被选择以最小化对下面的半导体衬底的损害的另一蚀刻暴露了半导体衬底的一部分。然后从半导体衬底的暴露部分生长外延半导体（28,66）以形成具有第一表面取向并且具有很少（如果有的话）缺陷的半导体区域。然后外延生长的半导体区域用于增强一种类型的晶体管，而第二表面取向的半导体层用于增强不同类型的晶体管。

25. 发明申请

US20070048919A1 Modified hybrid orientation technology 失效
标题翻译：改进的混合取向技术
公开(公告)号：US20070048919A1
公开(公告)日：2007-03-01
申请号：US11209869
申请日：2005-08-23
申请人： Olubunmi Adetutu , Mariam Sadaka , Ted White , Bich-Yen Nguyen
发明人： Olubunmi Adetutu , Mariam Sadaka , Ted White , Bich-Yen Nguyen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823878 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L27/1207
摘要： A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). By forming the first gate electrode (151) over a first SOI substrate (90) formed by depositing (100) silicon and forming the second gate electrode (161) over an epitaxially grown (110) SiGe substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.
摘要翻译：半导体工艺和装置包括通过在第一高k栅极电介质（121）上形成第一栅极电极（151）并在第二栅极电极（121）上形成第二栅极电极（151）而在混合衬底（17）上形成第一和第二金属栅电极（151,161）电极（161）在与第一栅极电介质（121）不同的至少第二高k栅极电介质（122）之上。通过在通过在外延生长（110）SiGe衬底（70）上沉积（100）硅并形成第二栅电极（161）而形成的第一SOI衬底（90）上形成第一栅电极（151），高性能CMOS 获得包括具有改善的空穴迁移率的高k金属PMOS栅电极（161）的器件。

26. 发明申请

US20070082453A1 METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE USING SILICON GERMANIUM 有权
标题翻译：使用硅锗制备半导体结构的方法
公开(公告)号：US20070082453A1
公开(公告)日：2007-04-12
申请号：US11609664
申请日：2006-12-12
申请人： Marius Orlowski , Alexander Barr , Mariam Sadaka , Ted White
发明人： Marius Orlowski , Alexander Barr , Mariam Sadaka , Ted White
IPC分类号： H01L21/20
CPC分类号： H01L29/1054 , H01L21/02126 , H01L21/02164 , H01L21/02236 , H01L21/31658 , H01L21/32105 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , Y10S438/933
摘要： A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.
摘要翻译：提供了具有硅层的半导体衬底。在一个实施例中，衬底是具有在硅层下面的氧化物层的绝缘体上硅（SOI）衬底。在硅层上形成非晶或多晶硅锗层。或者，将锗注入硅层的顶部以形成非晶硅锗层。然后氧化硅锗层以将硅锗层转化为二氧化硅层，并将至少一部分硅层转化为富含锗的硅。然后在使用富含锗的硅形成晶体管之前去除二氧化硅层。在一个实施例中，使用硅层上方的图案化掩模层和硅锗层选择性地形成富锗富硅。或者，可以使用隔离区来限定其中形成富锗的硅的衬底的局部区域。

27. 发明申请

US20050245092A1 Method for making a semiconductor structure using silicon germanium 有权
标题翻译：使用硅锗制造半导体结构的方法
公开(公告)号：US20050245092A1
公开(公告)日：2005-11-03
申请号：US10836172
申请日：2004-04-30
申请人： Marius Orlowski , Alexander Barr , Mariam Sadaka , Ted White
发明人： Marius Orlowski , Alexander Barr , Mariam Sadaka , Ted White
IPC分类号： H01L21/31 , H01L21/316 , H01L21/321 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/10
CPC分类号： H01L29/1054 , H01L21/02126 , H01L21/02164 , H01L21/02236 , H01L21/31658 , H01L21/32105 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , Y10S438/933
摘要： A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.
摘要翻译：提供了具有硅层的半导体衬底。在一个实施例中，衬底是具有在硅层下面的氧化物层的绝缘体上硅（SOI）衬底。在硅层上形成非晶或多晶硅锗层。或者，将锗注入硅层的顶部以形成非晶硅锗层。然后氧化硅锗层以将硅锗层转化为二氧化硅层，并将至少一部分硅层转化为富含锗的硅。然后在使用富含锗的硅形成晶体管之前去除二氧化硅层。在一个实施例中，使用硅层上方的图案化掩模层和硅锗层选择性地形成富锗富硅。或者，可以使用隔离区来限定其中形成富锗的硅的衬底的局部区域。

28. 发明授权

US08617925B2 Methods of forming bonded semiconductor structures in 3D integration processes using recoverable substrates, and bonded semiconductor structures formed by such methods 有权
标题翻译：在使用可恢复基板的3D积分处理中形成键合半导体结构的方法以及通过这些方法形成的结合的半导体结构
公开(公告)号：US08617925B2
公开(公告)日：2013-12-31
申请号：US13206280
申请日：2011-08-09
申请人： Mariam Sadaka , Bich-Yen Nguyen
发明人： Mariam Sadaka , Bich-Yen Nguyen
IPC分类号： H01L23/538 , H01L21/58 , H01L21/768
CPC分类号： H01L21/486 , H01L21/561 , H01L21/6835 , H01L21/76898 , H01L23/147 , H01L23/49827 , H01L24/06 , H01L24/08 , H01L24/80 , H01L24/97 , H01L25/0652 , H01L25/50 , H01L2221/68345 , H01L2224/05009 , H01L2224/08146 , H01L2224/08235 , H01L2224/80099 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2224/97 , H01L2225/06541 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/1461 , H01L2924/15311 , H01L2924/1816 , H01L2224/80 , H01L2224/03 , H01L2924/00
摘要： Methods of forming bonded semiconductor structures include forming through wafer interconnects through a layer of material of a first substrate structure, bonding one or more semiconductor structures over the layer of material, and electrically coupling the semiconductor structures with the through wafer interconnects. A second substrate structure may be bonded over the processed semiconductor structures on a side thereof opposite the first substrate structure. A portion of the first substrate structure then may be removed, leaving the layer of material with the through wafer interconnects therein attached to the processed semiconductor structures. At least one through wafer interconnects then may be electrically coupled to a conductive feature of another structure, after which the second substrate structure may be removed. Bonded semiconductor structures are formed using such methods.
摘要翻译：形成键合的半导体结构的方法包括通过晶片互连通过第一衬底结构的材料层形成，在材料层上结合一个或多个半导体结构，以及将半导体结构与贯穿晶片互连电连接。第二衬底结构可以在与第一衬底结构相对的一侧上结合在经处理的半导体结构上。然后可以去除第一衬底结构的一部分，留下其中附着有经处理的半导体结构的贯穿晶片互连的材料层。然后至少一个贯穿晶片互连可以电耦合到另一结构的导电特征，之后可以去除第二衬底结构。使用这种方法形成结合的半导体结构。

29. 发明申请

US20130015442A1 BONDED SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME 有权
标题翻译：粘结半导体结构及其形成方法
公开(公告)号：US20130015442A1
公开(公告)日：2013-01-17
申请号：US13637565
申请日：2011-02-22
申请人： Carlos Mazure , Bich-Yen Nguyen , Mariam Sadaka
发明人： Carlos Mazure , Bich-Yen Nguyen , Mariam Sadaka
IPC分类号： H01L29/04 , H01L29/06 , H01L21/302
CPC分类号： H01L27/0688 , H01L21/02532 , H01L21/0262 , H01L21/02667 , H01L21/187 , H01L21/8221 , H01L2924/00011 , H01L2224/80001
摘要： Methods of forming semiconductor structures include transferring a portion (116a) of a donor structure to a processed semiconductor structure (102) that includes at least one non-planar surface. An amorphous film (144) may be formed over at least one non-planar surface of the bonded semiconductor structure, and the amorphous film may be planarized to form one or more planarized surfaces. Semiconductor structures include a bonded semiconductor structure having at least one non-planar surface, and an amorphous film disposed over the at least one non-planar surface. The bonded semiconductor structure may include a processed semiconductor structure and a portion of a single crystal donor structure attached to a non-planar surface of the processed semiconductor structure.
摘要翻译：形成半导体结构的方法包括将施主结构的部分（116a）转移到包括至少一个非平面表面的经处理的半导体结构（102）。可以在结合的半导体结构的至少一个非平面表面上形成非晶膜（144），并且可以将非晶膜平坦化以形成一个或多个平坦化表面。半导体结构包括具有至少一个非平面表面的键合半导体结构和设置在所述至少一个非平面表面上的非晶膜。键合的半导体结构可以包括处理的半导体结构和附接到处理的半导体结构的非平面表面的单晶体施主结构的一部分。

30. 发明授权

US08058158B2 Hybrid semiconductor substrate including semiconductor-on-insulator region and method of making the same 有权
标题翻译：包括绝缘体上半导体区域的混合半导体衬底及其制造方法
公开(公告)号：US08058158B2
公开(公告)日：2011-11-15
申请号：US12726800
申请日：2010-03-18
申请人： Konstantin Bourdelle , Bich-Yen Nguyen , Mariam Sadaka
发明人： Konstantin Bourdelle , Bich-Yen Nguyen , Mariam Sadaka
IPC分类号： H01L21/425 , H01L21/70
CPC分类号： H01L21/2007 , H01L21/187 , H01L21/26513 , H01L21/823412 , H01L21/823481 , H01L27/1207
摘要： A method for manufacturing a hybrid semiconductor substrate comprises the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby, a higher number of process steps involved in the manufacturing process of hybrid semiconductor substrates may be avoided.
摘要翻译：一种用于制造混合半导体衬底的方法包括以下步骤：（a）提供包括绝缘体上半导体（SeOI）区域的混合半导体衬底，其包括在基底衬底上的绝缘层和绝缘层上的SeOI层，以及体半导体区域，其中所述SeOI区域和所述体半导体区域共享相同的基底基板; （b）在SeOI区域上提供掩模层; 和（c）通过同时掺杂SeOI区域和体半导体区域使得SeOI区域中的第一杂质水平包含在掩模内而形成第一杂质水平。因此，可以避免在混合半导体衬底的制造过程中涉及的更多数量的工艺步骤。

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