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21. 发明授权

US08264027B2 Printed non-volatile memory 有权
标题翻译：打印的非易失性存储器
公开(公告)号：US08264027B2
公开(公告)日：2012-09-11
申请号：US12723542
申请日：2010-03-12
申请人： Arvind Kamath , Patrick Smith , James Montague Cleeves
发明人： Arvind Kamath , Patrick Smith , James Montague Cleeves
IPC分类号： H01L29/788
CPC分类号： H01L21/28518 , H01L21/288 , H01L21/76801 , H01L21/76895 , H01L27/115 , H01L27/11558 , H01L27/1292 , H01L29/66757 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.
摘要翻译：公开了一种非易失性存储器单元，其具有在相同水平位置处并且间隔开预定距离的第一和第二半导体岛，所述第一半岛具有提供控制栅极和所述第二半岛岛提供源极和漏极端子; 在所述第一半导体岛的至少一部分上的栅介质层; 在所述第二半导体岛的至少一部分上的隧道介电层; 至少部分栅极电介质层和隧道电介质层上的浮栅; 以及与控制栅极以及源极和漏极端子电接触的金属层。在一个有利的实施例中，可以使用“全印刷”工艺技术来制造非易失性存储单元。

22. 发明申请

US20080048240A1 Printed Non-Volatile Memory 有权
标题翻译：印刷非易失性存储器
公开(公告)号：US20080048240A1
公开(公告)日：2008-02-28
申请号：US11842884
申请日：2007-08-21
申请人： Arvind Kamath , Patrick Smith , James Montague Cleeves
发明人： Arvind Kamath , Patrick Smith , James Montague Cleeves
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/28518 , H01L21/288 , H01L21/76801 , H01L21/76895 , H01L27/115 , H01L27/11558 , H01L27/1292 , H01L29/66757 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.
摘要翻译：公开了一种非易失性存储器单元，其具有在相同水平位置处并且间隔开预定距离的第一和第二半导体岛，所述第一半岛具有提供控制栅极和所述第二半岛岛提供源极和漏极端子; 在所述第一半导体岛的至少一部分上的栅介质层; 在所述第二半导体岛的至少一部分上的隧道介电层; 至少部分栅极电介质层和隧道电介质层上的浮栅; 以及与控制栅极以及源极和漏极端子电接触的金属层。在一个有利的实施例中，可以使用“全印刷”工艺技术来制造非易失性存储单元。

23. 发明申请

US20120307569A1 Printed Non-Volatile Memory 有权
标题翻译：印刷非易失性存储器
公开(公告)号：US20120307569A1
公开(公告)日：2012-12-06
申请号：US13585673
申请日：2012-08-14
申请人： Arvind KAMATH , Patrick Smith , James Montague Cleeves
发明人： Arvind KAMATH , Patrick Smith , James Montague Cleeves
IPC分类号： H01L29/788 , G11C16/10 , G11C16/04 , H01L21/336
CPC分类号： H01L21/28518 , H01L21/288 , H01L21/76801 , H01L21/76895 , H01L27/115 , H01L27/11558 , H01L27/1292 , H01L29/66757 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.
摘要翻译：公开了一种非易失性存储器单元，其具有在相同水平位置处并且间隔开预定距离的第一和第二半导体岛，所述第一半岛具有提供控制栅极和所述第二半岛岛提供源极和漏极端子; 在所述第一半导体岛的至少一部分上的栅介质层; 在所述第二半导体岛的至少一部分上的隧道介电层; 至少部分栅极电介质层和隧道电介质层上的浮栅; 以及与控制栅极以及源极和漏极端子电接触的金属层。在一个有利的实施例中，非易失性存储单元可以使用全印刷工艺技术来制造。

24. 发明申请

US20100244133A1 Printed Dopant Layers 有权
标题翻译：印刷掺杂层
公开(公告)号：US20100244133A1
公开(公告)日：2010-09-30
申请号：US12797274
申请日：2010-06-09
申请人： Arvind KAMATH , James Montague Cleeves , Joerg Rockenberger , Patrick Smith , Fabio Zürcher
发明人： Arvind KAMATH , James Montague Cleeves , Joerg Rockenberger , Patrick Smith , Fabio Zürcher
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/316 , H01L21/02211 , H01L21/02288 , H01L21/02318 , H01L21/3165 , H01L27/1285 , H01L27/1292 , H01L29/66757 , H01L29/78621
摘要： A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.
摘要翻译：一种用于制造诸如MOS晶体管的电子器件的方法，包括以下步骤：在电功能衬底上形成多个半导体岛，在第一半导体岛子集上或第二子体上印刷第一电介质层，在半导体岛的第二子集上或之上，以及退火。第一介电层包含第一掺杂剂，并且（任选的）第二介电层包含不同于第一掺杂剂的第二掺杂剂。电介质层，半导体岛和衬底被充分退火以将第一掺杂剂扩散到半导体岛的第一子集中，并且当存在时将第二掺杂剂扩散到半导体岛的第二子集中。

25. 发明授权

US08758982B1 Laser processing enabling radio frequency identification (RFID) customization 有权
标题翻译：激光加工使射频识别（RFID）定制
公开(公告)号：US08758982B1
公开(公告)日：2014-06-24
申请号：US11595839
申请日：2006-11-08
申请人： Criswell Choi , Patrick Smith , James Montague Cleeves , Joerg Rockenberger , Christopher Gudeman , J. Devin MacKenzie
发明人： Criswell Choi , Patrick Smith , James Montague Cleeves , Joerg Rockenberger , Christopher Gudeman , J. Devin MacKenzie
IPC分类号： G03F7/00
CPC分类号： G06K19/07773 , G03F7/0043 , G03F7/2055 , G06K19/07749 , G08B13/2402 , G08B13/2417 , G08B13/244 , G08B13/2468
摘要： Methods, algorithms, processes, circuits, and/or structures for laser patterning suitable for customized RFID designs are disclosed. In one embodiment, a method of laser patterning of an identification device can include the steps of: (i) depositing a patternable resist formulation on a substrate having configurable elements and/or materials thereon; (ii) irradiating the resist formulation with a laser tool sufficiently to change the solubility characteristics of the resist in a developer; and (iii) developing exposed areas of the resist using the developer. Embodiments of the present invention can advantageously provide a relatively low cost and high throughput approach for customized RFID devices.
摘要翻译：公开了适用于定制RFID设计的用于激光图案的方法，算法，过程，电路和/或结构。在一个实施例中，识别装置的激光图案化的方法可以包括以下步骤：（i）在其上具有可配置元件和/或材料的衬底上沉积可图案化的抗蚀剂制剂; （ii）用激光工具照射抗蚀剂制剂，足以改变显影剂中抗蚀剂的溶解度特性; 和（iii）使用显影剂显影抗蚀剂的曝光区域。本发明的实施例可以有利地为定制的RFID设备提供相对低成本和高吞吐量的方法。

26. 发明授权

US08426905B2 Profile engineered, electrically active thin film devices 有权
标题翻译：型材设计，电活性薄膜器件
公开(公告)号：US08426905B2
公开(公告)日：2013-04-23
申请号：US12243880
申请日：2008-10-01
申请人： Arvind Kamath , Erik Scher , Patrick Smith , Aditi Chandra , Steven Molesa
发明人： Arvind Kamath , Erik Scher , Patrick Smith , Aditi Chandra , Steven Molesa
IPC分类号： H01L29/788
CPC分类号： H01L21/36 , C23C18/08 , C23C18/122 , C23C18/1245 , C23C18/1295 , H01L21/02532 , H01L21/02601 , H01L21/02628 , H01L21/28273 , H01L21/28518 , H01L21/288 , H01L21/76871 , H01L21/76895 , H01L27/1285 , H01L27/1292 , H01L28/40 , H01L29/0657 , H01L29/66143 , H01L29/6675 , H01L29/7881 , H01L29/872 , H05K1/16 , H05K1/162 , H05K3/125 , H05K2201/098
摘要： The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.
摘要翻译：本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

27. 发明授权

US08822301B2 Profile engineered thin film devices and structures 有权
标题翻译：型材设计薄膜器件和结构
公开(公告)号：US08822301B2
公开(公告)日：2014-09-02
申请号：US13791721
申请日：2013-03-08
申请人： Arvind Kamath , Erik Scher , Patrick Smith , Aditi Chandra , Steven Molesa
发明人： Arvind Kamath , Erik Scher , Patrick Smith , Aditi Chandra , Steven Molesa
IPC分类号： H01L21/20
CPC分类号： H01L21/36 , C23C18/08 , C23C18/122 , C23C18/1245 , C23C18/1295 , H01L21/02532 , H01L21/02601 , H01L21/02628 , H01L21/28273 , H01L21/28518 , H01L21/288 , H01L21/76871 , H01L21/76895 , H01L27/1285 , H01L27/1292 , H01L28/40 , H01L29/0657 , H01L29/66143 , H01L29/6675 , H01L29/7881 , H01L29/872 , H05K1/16 , H05K1/162 , H05K3/125 , H05K2201/098
摘要： The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.
摘要翻译：本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

28. 发明授权

US08973231B1 Methods for forming electrically precise capacitors, and structures formed therefrom 有权
标题翻译：用于形成电精密电容器的方法和由其形成的结构
公开(公告)号：US08973231B1
公开(公告)日：2015-03-10
申请号：US13868916
申请日：2013-04-23
申请人： Arvind Kamath , Criswell Choi , Patrick Smith , Erik Scher , Jiang Li
发明人： Arvind Kamath , Criswell Choi , Patrick Smith , Erik Scher , Jiang Li
IPC分类号： H01G4/06 , H01G4/01 , H01G13/00
CPC分类号： H01G4/40 , H01G4/002 , H01G4/005 , H01G4/008 , H01G4/01 , H01G4/10 , H01G4/1209 , H01G4/224 , H01G4/30 , H01G4/306 , H01G4/33 , H01G13/00 , H01L23/66 , H01L27/016 , H01L28/60 , H01L2223/6677 , H01Q1/22 , H01Q1/2283 , H01Q1/38 , Y10T29/43 , Y10T29/435 , Y10T29/49002 , Y10T29/49016
摘要： High precision capacitors and methods for forming the same utilizing a precise and highly conformal deposition process for depositing an insulating layer on substrates of various roughness and composition are disclosed. The method generally includes the steps of depositing a first insulating layer on a metal substrate by atomic layer deposition (ALD); (b) forming a first capacitor electrode on the first insulating layer; and (c) forming a second insulating layer on the first insulating layer and on or adjacent to the first capacitor electrode. The methods provide an improved deposition process that produces a highly conformal insulating layer on a wide range of substrates, and thereby, an improved capacitor.
摘要翻译：公开了一种高精度电容器及其形成方法，其利用精确且高度保形的沉积工艺在绝缘层上沉积各种粗糙度和组成的衬底。该方法通常包括以下步骤：通过原子层沉积（ALD）在金属衬底上沉积第一绝缘层; （b）在所述第一绝缘层上形成第一电容器电极; 和（c）在所述第一绝缘层上形成第二绝缘层，并且在所述第一电容器电极上或与所述第一电容器电极相邻。这些方法提供了一种改进的沉积工艺，其在宽范围的衬底上产生高度保形的绝缘层，从而产生改进的电容器。

29. 发明授权

US08446706B1 High precision capacitors 有权
标题翻译：高精度电容器
公开(公告)号：US08446706B1
公开(公告)日：2013-05-21
申请号：US12249841
申请日：2008-10-10
申请人： Arvind Kamath , Criswell Choi , Patrick Smith , Erik Scher , Jiang Li
发明人： Arvind Kamath , Criswell Choi , Patrick Smith , Erik Scher , Jiang Li
IPC分类号： H01G4/06 , H01G4/005
CPC分类号： H01G4/40 , H01G4/002 , H01G4/005 , H01G4/008 , H01G4/01 , H01G4/10 , H01G4/1209 , H01G4/224 , H01G4/30 , H01G4/306 , H01G4/33 , H01G13/00 , H01L23/66 , H01L27/016 , H01L28/60 , H01L2223/6677 , H01Q1/22 , H01Q1/2283 , H01Q1/38 , Y10T29/43 , Y10T29/435 , Y10T29/49002 , Y10T29/49016
摘要： High precision capacitors and methods for forming the same utilizing a precise and highly conformal deposition process for depositing an insulating layer on substrates of various roughness and composition. The method generally comprises the steps of depositing a first insulating layer on a metal substrate by atomic layer deposition (ALD); (b) forming a first capacitor electrode on the first insulating layer; and (c) forming a second insulating layer on the first insulating layer and on or adjacent to the first capacitor electrode. Embodiments provide an improved deposition process that produces a highly conformal insulating layer on a wide range of substrates, and thereby, an improved capacitor.
摘要翻译：高精度电容器及其形成方法采用精确且高度保形的沉积工艺，用于在各种粗糙度和组成的基底上沉积绝缘层。该方法通常包括以下步骤：通过原子层沉积（ALD）在金属衬底上沉积第一绝缘层; （b）在所述第一绝缘层上形成第一电容器电极; 和（c）在所述第一绝缘层上形成第二绝缘层，并且在所述第一电容器电极上或与所述第一电容器电极相邻。实施例提供了一种改进的沉积工艺，其在宽范围的衬底上产生高度保形的绝缘层，从而产生改进的电容器。

30. 发明授权

US08891264B1 Series circuits and devices 有权
标题翻译：串联电路和器件
公开(公告)号：US08891264B1
公开(公告)日：2014-11-18
申请号：US11940161
申请日：2007-11-14
申请人： James Montague Cleeves , Patrick Smith
发明人： James Montague Cleeves , Patrick Smith
IPC分类号： H02H7/125 , H02H7/127
CPC分类号： G06K19/0701 , H01L27/0266 , Y02P80/30
摘要： Embodiments of the present invention relate to a rectifier circuit and methods of making the same for use in wireless devices (e.g., RFID tags). The present invention is drawn to a rectifier circuit comprising first and second diode-wired transistors in series, each having a gate oxide layers of the same target thickness. The first diode-wired transistor receives an alternating current and the second diode-wired transistor provides a rectifier output. The first and second diode-wired transistors are configured to divide between them a first voltage differential across the rectifier circuit. The gate oxides are exposed to a peak stress that is similar to a stress on the gate oxide of logic transistors made using the same process. The present invention is further drawn to a method of making a rectifier circuit, comprising printing a plurality of transistor bodies on a substrate, forming a gate oxide on each of the transistor bodies and a gate on each gate oxide, doping exposed portions of the transistor body to form first and second source/drain terminals therein, and forming interconnects electrically connecting the first source/drain terminals to the gate over the corresponding transistor body.
摘要翻译：本发明的实施例涉及一种整流电路及其制造方法，用于无线设备（例如RFID标签）。本发明涉及一种包括串联的第一和第二二极管接线晶体管的整流电路，每个具有相同目标厚度的栅氧化层。第一二极管接线晶体管接收交流电流，第二二极管接线晶体管提供整流器输出。第一和第二二极管接线晶体管被配置为在它们之间划分整流器电路两端的第一电压差。栅极氧化物暴露于与使用相同工艺制造的逻辑晶体管的栅极氧化物上的应力相似的峰值应力。本发明进一步涉及一种制造整流器电路的方法，包括在衬底上印刷多个晶体管本体，在每个晶体管本体上形成栅极氧化物，并在每个栅极氧化物上形成栅极，掺杂晶体管的暴露部分从而在其中形成第一和第二源极/漏极端子，以及形成将第一源极/漏极端子电连接到相应晶体管本体上的栅极的互连。

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