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21. 发明授权

US06677235B1 Silicon die with metal feed through structure 有权
标题翻译：硅晶片采用金属进料结构
公开(公告)号：US06677235B1
公开(公告)日：2004-01-13
申请号：US10004977
申请日：2001-12-03
申请人： Visvamohan Yegnashankaran , Gobi R. Padmanabhan
发明人： Visvamohan Yegnashankaran , Gobi R. Padmanabhan
IPC分类号： H01L2144
CPC分类号： H01L21/76898 , H01L21/76838 , H01L2224/48227 , H01L2924/00013 , H01L2924/01078 , H01L2924/04941 , H01L2924/10253 , H01L2924/15311 , H01L2924/30107 , H01L2224/29099 , H01L2924/00
摘要： A semiconductor die is formed in a process that forms a trench opening in the semiconductor material prior to the formation of the contacts and the metal-1 layer. When contacts are then formed to contact circuit structures, such as a doped region in the top surface of the semiconductor material, a trench contact is formed that fills up the trench opening. During the final steps of the process, the back side of the semiconductor material is ground down to expose the trench contact.
摘要翻译：在形成触点和金属-1层之前，在半导体材料中形成沟槽开口的工艺中形成半导体管芯。然后当接触形成为接触电路结构时，例如半导体材料的顶表面中的掺杂区域，形成填充沟槽开口的沟槽接触。在该工艺的最后步骤期间，将半导体材料的背面磨平以暴露沟槽接触。

22. 发明授权

US09941886B2 Integrated circuit (IC) chip comprising an identification circuit 有权
公开(公告)号：US09941886B2
公开(公告)日：2018-04-10
申请号：US15675705
申请日：2017-08-12
申请人： Jimmy Yong Xiao , Surendra Kumar Rathaur , Visvamohan Yegnashankaran
发明人： Jimmy Yong Xiao , Surendra Kumar Rathaur , Visvamohan Yegnashankaran
IPC分类号： H03K19/094 , H01L23/544
CPC分类号： H03K19/094 , H01L23/544 , H01L2223/54433 , H01L2224/49113 , H01L2924/00 , H01L2924/00014 , H01L2924/13091
摘要： An embodiment of the present invention is an identification circuit for generating an identification number (ID). The identification circuit includes a plurality of identification cells each comprising a latch having a first output and a second output that are opposite to each other. The first output and the second output are a function of process variations of the identification circuit. A first buffer and a second buffer are provided on both sides of the latch and connected to the first output and the second output of the latch, respectively.

23. 发明授权

US08303484B2 Self-propelled robotic device that moves through bodily and other passageways 有权
标题翻译：通过身体和其他通道移动的自行式机器人装置
公开(公告)号：US08303484B2
公开(公告)日：2012-11-06
申请号：US12621719
申请日：2009-11-19
申请人： Peter J. Hopper , Philipp Lindorfer , William French , Visvamohan Yegnashankaran
发明人： Peter J. Hopper , Philipp Lindorfer , William French , Visvamohan Yegnashankaran
IPC分类号： A61B1/00
CPC分类号： A61B1/041 , A61B1/00082 , A61B1/00156 , A61B1/005 , A61B1/31 , A61B8/12 , A61B8/429 , A61B8/4472
摘要： A self-propelled robotic device moves through bodily and other passageways by inflating regions of an overlying bladder along the length of the robotic device in a sequence that imparts motion to the device. The regions of the overlying bladder are inflated by energizing a plurality of coils, which are surrounded by a ferrofluid, in a sequence. The ferrofluid responds to the magnetic field created by an energized coil by creating a bulge in the side wall of the overlying bladder.
摘要翻译：自动推进的机器人装置通过身体和其他通道沿着机器人装置的长度沿着向装置施加运动的顺序使覆盖的膀胱的区域膨胀而移动。通过对由铁磁流体包围的多个线圈进行顺序地激励上覆的气囊的区域来充气。铁磁流体通过在上覆气囊的侧壁中产生凸起来响应由通电线圈产生的磁场。

24. 发明授权

US07790602B1 Method of forming a metal interconnect with capacitive structures that adjust the capacitance of the interconnect 有权
标题翻译：用调整互连电容的电容结构形成金属互连的方法
公开(公告)号：US07790602B1
公开(公告)日：2010-09-07
申请号：US11372830
申请日：2006-03-09
申请人： Visvamohan Yegnashankaran , Gobi R. Padmanabhan
发明人： Visvamohan Yegnashankaran , Gobi R. Padmanabhan
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method of forming capacitive structures in trenches which have been formed in a multilevel metal interconnect structure is disclosed. The method of forming the capacitive structures allows the capacitance of the multilevel metal interconnect structure to be adjusted, and thereby optimized, to respond to signals from devices that are formed on an underlying substrate.
摘要翻译：公开了一种在多层金属互连结构中形成的沟槽中形成电容结构的方法。形成电容结构的方法允许调整多层金属互连结构的电容，从而优化，以响应来自形成在下面的衬底上的器件的信号。

25. 发明授权

US07329555B1 Method of selectively forming MEMS-based semiconductor devices at the end of a common fabrication process 有权
标题翻译：在公共制造工艺结束时选择性地形成MEMS基半导体器件的方法
公开(公告)号：US07329555B1
公开(公告)日：2008-02-12
申请号：US10894846
申请日：2004-07-20
申请人： Gobi R. Padmanabhan , Visvamohan Yegnashankaran
发明人： Gobi R. Padmanabhan , Visvamohan Yegnashankaran
IPC分类号： H01L21/00
CPC分类号： B81C1/00246
摘要： Various semiconductor devices can be formed at the end of a common fabrication process, thereby significantly improving manufacturing flexibility, by selectively wiring bonding different CMOS circuits to different MEMS, which are formed on the same semiconductor die. A semiconductor device that has a number of CMOS circuits and a number of MEMS is formed on the same semiconductor wafer in adjacent regions on the wafer, and then diced such that the CMOS circuits and the MEMS are formed on the same die. After dicing, different CMOS circuits and different MEMS can be selectively connected during the wire bonding step to form the different semiconductor devices.
摘要翻译：可以在公共制造工艺的结束时形成各种半导体器件，从而通过选择性地将不同的CMOS电路布线到形成在相同的半导体管芯上的不同MEMS上，从而显着提高制造灵活性。具有多个CMOS电路和多个MEMS的半导体器件形成在晶片上的相邻区域的同一半导体晶片上，然后进行切割，使得CMOS电路和MEMS形成在同一裸片上。在切割之后，在引线接合步骤期间可以选择性地连接不同的CMOS电路和不同的MEMS，以形成不同的半导体器件。

26. 发明授权

US07230301B1 Single-crystal silicon semiconductor structure 有权
标题翻译：单晶硅半导体结构
公开(公告)号：US07230301B1
公开(公告)日：2007-06-12
申请号：US10884910
申请日：2004-07-06
申请人： Gobi R. Padmanabhan , Visvamohan Yegnashankaran
发明人： Gobi R. Padmanabhan , Visvamohan Yegnashankaran
IPC分类号： H01L27/01
CPC分类号： H01L29/6659 , H01L29/66825 , H01L29/7833 , H01L29/7881 , H01L29/8605 , H01L29/94
摘要： A resistor, a transistor, and a capacitor can be fabricated on a semiconductor wafer in a process that forms an isolated single-crystal region with precise dimensions. The isolated single-crystal region, in turn, defines the body of the resistor, the gate of the transistor, and the top plate of the capacitor.
摘要翻译：可以在形成具有精确尺寸的隔离单晶区域的工艺中在半导体晶片上制造电阻器，晶体管和电容器。隔离的单晶区域又定义了电阻体的主体，晶体管的栅极和电容器的顶板。

27. 发明授权

US06946321B1 Method of forming the integrated circuit having a die with high Q inductors and capacitors attached to a die with a circuit as a flip chip 有权
标题翻译：形成集成电路的方法，该集成电路具有具有高Q电感器的模具和附接到芯片的电容器，其中电路作为倒装芯片
公开(公告)号：US06946321B1
公开(公告)日：2005-09-20
申请号：US10853875
申请日：2004-05-26
申请人： Visvamohan Yegnashankaran , Gobi R. Padmanabhan
发明人： Visvamohan Yegnashankaran , Gobi R. Padmanabhan
IPC分类号： H01F17/00 , H01F27/29 , H01L21/60 , H01L23/16 , H01L23/49 , H01L23/66
CPC分类号： H01L23/66 , H01F17/0006 , H01F27/292 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/16145 , H01L2224/32145 , H01L2224/48091 , H01L2224/49112 , H01L2224/49171 , H01L2224/49175 , H01L2224/49179 , H01L2924/00014 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , H01L2924/30105 , H01L2924/30107 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor integrated circuit with high Q inductors and capacitors is disclosed. A semiconductor electrical circuit is formed on a first die, while micro-electromechanical structures having inductance and capacitance are formed on a second die. The second die is attached and electrically connected to the first die as a flip chip.
摘要翻译：公开了一种具有高Q电感和电容器的半导体集成电路。半导体电路形成在第一管芯上，而具有电感和电容的微机电结构形成在第二管芯上。第二管芯作为倒装芯片被附接并电连接到第一管芯。

28. 发明授权

US06933212B1 Apparatus and method for dicing semiconductor wafers 有权
标题翻译：用于切割半导体晶片的装置和方法
公开(公告)号：US06933212B1
公开(公告)日：2005-08-23
申请号：US10757303
申请日：2004-01-13
申请人： Shaw Wei Lee , Nghia T. Tu , Sadanand Patil , Visvamohan Yegnashankaran
发明人： Shaw Wei Lee , Nghia T. Tu , Sadanand Patil , Visvamohan Yegnashankaran
IPC分类号： H01L21/301
CPC分类号： H01L21/78
摘要： A method and apparatus for the dicing of semiconductor wafers using pressure to mechanically separate the individual die from the wafer without the use of a wafer saw. The method includes forming trenches along the scribe lines on a semiconductor wafer and then applying a mechanical pressure to the semiconductor wafer. The mechanical pressure causes a “clean break” of the wafer along the scribe lines, thereby singulating individual die on the wafer. The apparatus comprises a pad for supporting a semiconductor wafer and a positioning member to position the semiconductor wafer on the pad. A pressure mechanism is provided to apply a mechanical pressure to the wafer so as to singulate the individual die on the wafer.
摘要翻译：一种用于使用压力切割半导体晶片的方法和装置，以在不使用晶片锯的情况下将单独的管芯与晶片机械分离。该方法包括沿着半导体晶片上的划线形成沟槽，然后向半导体晶片施加机械压力。机械压力导致晶片沿着划线的“干净的断裂”，从而在晶片上分离单独的芯片。该装置包括用于支撑半导体晶片的焊盘和用于将半导体晶片定位在焊盘上的定位构件。提供压力机构以向晶片施加机械压力，以将晶片上的单个管芯分离。

29. 发明授权

US06746956B1 Hermetic seal for silicon die with metal feed through structure 有权
标题翻译：硅胶密封用金属进料通过结构
公开(公告)号：US06746956B1
公开(公告)日：2004-06-08
申请号：US10170506
申请日：2002-06-13
申请人： Gobi R. Padmanabhan , Visvamohan Yegnashankaran
发明人： Gobi R. Padmanabhan , Visvamohan Yegnashankaran
IPC分类号： H01L21302
CPC分类号： H01L21/76898 , H01L21/76838 , H01L2224/48227 , H01L2924/00013 , H01L2924/01078 , H01L2924/04941 , H01L2924/10253 , H01L2924/15311 , H01L2924/30107 , H01L2224/29099 , H01L2924/00
摘要： A semiconductor die is formed in a process that forms a trench opening in the semiconductor material prior to the formation of the contacts and the metal-1 layer. When contacts are then formed to contact circuit structures, such as a doped region in the top surface of the semiconductor material, a trench contact is formed that fills up the trench opening. During the final steps of the process, the back side of the semiconductor material is ground down to expose the trench contact. The wafer is cut to form a plurality of dice, and the exposed edges of the dice are protected.
摘要翻译：在形成触点和金属-1层之前，在半导体材料中形成沟槽开口的工艺中形成半导体管芯。然后当接触形成为接触电路结构时，例如半导体材料的顶表面中的掺杂区域，形成填充沟槽开口的沟槽接触。在该工艺的最后步骤期间，将半导体材料的背面磨平以暴露沟槽接触。切割晶片以形成多个骰子，并且保护骰子的暴露边缘。

30. 发明授权

US06730969B1 Radiation hardened MOS transistor 有权
标题翻译：辐射硬化MOS晶体管
公开(公告)号：US06730969B1
公开(公告)日：2004-05-04
申请号：US10185927
申请日：2002-06-27
申请人： Gobi R. Padmanabhan , Visvamohan Yegnashankaran , Reda Razouk
发明人： Gobi R. Padmanabhan , Visvamohan Yegnashankaran , Reda Razouk
IPC分类号： H01L2362
CPC分类号： H01L29/4238 , H01L23/4824 , H01L29/0692 , H01L2924/0002 , H01L2924/00
摘要： The drain-to-source field leakage current and the device-to-device field leakage current that are caused by radiation-induced hole trapping in the field oxide region are reduced in the present invention by forming the source and drain regions a distance apart from the edge of the field oxide region.
摘要翻译：在本发明中，通过形成源极和漏极区域的距离减小了在场氧化物区域中由辐射诱发的空穴俘获引起的漏 - 源场漏电流和器件到器件场漏电流场氧化物区域的边缘。

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