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21. 发明授权

US06507061B1 Multiple layer phase-change memory 有权
公开(公告)号：US06507061B1
公开(公告)日：2003-01-14
申请号：US09945331
申请日：2001-08-31
申请人： Stephen J. Hudgens , Tyler A. Lowrey , Patrick J. Klersy
发明人： Stephen J. Hudgens , Tyler A. Lowrey , Patrick J. Klersy
IPC分类号： H01L2976
CPC分类号： H01L45/06 , H01L29/8615 , H01L45/1233 , H01L45/128 , H01L45/144
摘要： A phase-change memory may be formed with at least two phase-change material layers separated by a barrier layer. The use of more than one phase-change layer enables a reduction in the programming volume while still providing adequate thermal insulation.

22. 发明授权

US06462984B1 Biasing scheme of floating unselected wordlines and bitlines of a diode-based memory array 有权
标题翻译：基于二极管的存储器阵列的浮动未选择字线和位线的偏置方案
公开(公告)号：US06462984B1
公开(公告)日：2002-10-08
申请号：US09895599
申请日：2001-06-29
申请人： Daniel Xu , Tyler A. Lowrey , David L. Kencke
发明人： Daniel Xu , Tyler A. Lowrey , David L. Kencke
IPC分类号： G11C1136
CPC分类号： G11C13/003 , G11C8/08 , G11C11/36 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C2013/0078 , G11C2213/72 , G11C2213/74 , G11C2213/76
摘要： An integrated circuit (IC) has a number of memory cells, each of which has a diode structure coupled between a bitline and a wordline that are selected when programming that cell. A target memory cell of the IC is programmed while simultaneously floating a number of unselected bitlines and wordlines in the IC.
摘要翻译：集成电路（IC）具有多个存储单元，每个存储单元具有耦合在编程该单元时选择的位线和字线之间的二极管结构。 IC的目标存储单元被编程，同时浮置IC中的多个未选定的位线和字线。

23. 发明授权

US06452223B1 Methods of fabricating buried digit lines and semiconductor devices including same 有权
公开(公告)号：US06452223B1
公开(公告)日：2002-09-17
申请号：US09651861
申请日：2000-08-30
申请人： Tyler A. Lowrey
发明人： Tyler A. Lowrey
IPC分类号： H01L27108
CPC分类号： H01L21/76897 , H01L21/76838 , H01L27/105 , H01L27/1052 , H01L27/10811 , H01L27/10885 , H01L27/10888
摘要： A method of electrically linking the contacts of a semiconductor device to their corresponding digit lines. The method includes disposing a quantity of mask material into a trench through which the contact is exposed. The mask also abuts a connect region of a conductive element of a corresponding digit line and, therefore, protrudes somewhat over a surface of the semiconductor device. A layer of insulative material is disposed over the semiconductor device with the mask material being exposed therethrough. The mask material is then removed, leaving open cavities that include the trench and a strap region continuous with the trench and with a connect region of the corresponding digit line. Conductive material is disposed within the cavity and electrically isolated from conductive material disposed in adjacent cavities, which define conductive plugs or studs and conductive straps from the conductive material. These plugs or studs and straps provide an electrically conductive link between each contact of the semiconductor device and its corresponding digit line. Semiconductor devices that include features that have been fabricated in accordance with the method of the present invention are also within the scope of the present invention.

24. 发明授权

US06423620B1 SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY DRAM CIRCUITRY 有权
公开(公告)号：US06423620B1
公开(公告)日：2002-07-23
申请号：US09935474
申请日：2001-08-21
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L2144
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

25. 发明授权

US06406954B1 Method for forming out-diffusing a dopant from the doped polysilicon into the N-type and P-type doped portion 失效
标题翻译：用于将掺杂剂从掺杂多晶硅扩散到N型和P型掺杂部分中的方法
公开(公告)号：US06406954B1
公开(公告)日：2002-06-18
申请号：US09388559
申请日：1999-09-02
申请人： Shubneesh Batra , Luan C. Tran , Tyler A. Lowrey
发明人： Shubneesh Batra , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , H01L21/823814
摘要： In one aspect, the invention includes a semiconductor processing method of diffusing dopant into both n-type and p-type doped regions of a semiconductive substrate. A semiconductive material is provided. The semiconductive material has a first portion and a second portion. The first portion is a p-type doped portion and the second portion is an n-type doped portion. A mask material is formed over the p-type and n-type doped portions. A first opening is formed to extend through the mask material and to the n-type doped portion. A second opening is formed to extend through the mask material and to the p-type doped portion. Conductively doped polysilicon is formed within the first and second openings. Dopant is out-diffused from the conductively-doped polysilicon and into the n-type and p-type doped portions. In another aspect, the invention includes methods of forming CMOS constructions. In yet another aspect, the invention encompasses methods of forming DRAM constructions.
摘要翻译：一方面，本发明包括将掺杂剂扩散到半导体衬底的n型和p型掺杂区域中的半导体处理方法。提供半导体材料。半导体材料具有第一部分和第二部分。第一部分是p型掺杂部分，第二部分是n型掺杂部分。在p型和n型掺杂部分上形成掩模材料。形成第一开口以延伸穿过掩模材料和n型掺杂部分。形成第二开口以延伸穿过掩模材料和p型掺杂部分。导电掺杂多晶硅形成在第一和第二开口内。掺杂剂从导电掺杂多晶硅扩散到n型和p型掺杂部分。另一方面，本发明包括形成CMOS结构的方法。在另一方面，本发明包括形成DRAM结构的方法。

26. 发明授权

US06194746B1 Vertical diode structures with low series resistance 有权
标题翻译：具有低串联电阻的垂直二极管结构
公开(公告)号：US06194746B1
公开(公告)日：2001-02-27
申请号：US09150317
申请日：1998-09-09
申请人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
发明人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
IPC分类号： H01L2100
CPC分类号： H01L29/66136 , H01L27/0814 , H01L29/861 , Y10S257/91 , Y10S438/979
摘要： A vertical diode is provided having a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
摘要翻译：提供了具有延伸穿过绝缘层并与硅晶片上的有源区接触的二极管开口的垂直二极管。硅化钛层覆盖二极管开口的内表面并接触有源区。二极管开口最初填充有非晶硅插塞，其在沉积期间被掺杂，随后再结晶以形成大晶粒多晶硅。硅插头具有重掺杂有第一类型掺杂剂的顶部部分和轻掺杂有第二类型掺杂剂的底部部分。顶部由底部界定，以便不与硅化钛层接触。对于垂直二极管的一个实施例，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

27. 发明授权

US5849635A Semiconductor processing method of forming an insulating dielectric layer and a contact opening therein 失效
标题翻译：在其中形成绝缘介电层和接触开口的半导体加工方法
公开(公告)号：US5849635A
公开(公告)日：1998-12-15
申请号：US680790
申请日：1996-07-11
申请人： Salman Akram , Tyler A. Lowrey
发明人： Salman Akram , Tyler A. Lowrey
IPC分类号： H01L21/311 , H01L21/316 , H01L21/768 , H01L21/44 , B05D1/36
CPC分类号： H01L21/02274 , H01L21/02164 , H01L21/31111 , H01L21/31612 , H01L21/31625 , H01L21/76802
摘要： A semiconductor processing method of forming a contact opening includes providing a substrate having a node location to which electrical connection is to be made. A layer comprising doped silicon dioxide is formed over the node location. Thereafter, both O.sub.2 and O.sub.3 are flowed simultaneously to the substrate along with tetraethylorthosilicate to the substrate to form a continuous layer comprising undoped silicon dioxide on the layer comprising doped silicon dioxide. During the flowing, a ratio of O.sub.3 to O.sub.2 flows is increased to form an outer portion of the continuous layer comprising undoped silicon dioxide to have a higher etch rate for a selected wet etch chemistry than an inner portion of said continuous layer. A common contact opening is anisotropically dry etched into the layer comprising undoped silicon dioxide and into the layer comprising doped silicon dioxide over the node location to outwardly expose the node location. After this etching, a subsequent wet etching with the selected chemistry is conducted within the common contact opening to widen the contact opening in the outer portion of the layer comprising undoped silicon dioxide as compared to the inner portion of the layer comprising undoped silicon dioxide. The subsequent wet etching is chosen and conducted to be effectively selective to not substantially laterally etch the layer comprising doped silicon dioxide.
摘要翻译：形成接触开口的半导体处理方法包括提供具有要与其进行电连接的节点位置的衬底。在节点位置形成包含掺杂二氧化硅的层。此后，O 2和O 3都与原硅酸四乙酯同时流动到衬底，以在包含掺杂二氧化硅的层上形成包含未掺杂的二氧化硅的连续层。在流动期间，增加O 3与O 2流量的比例，以形成包含未掺杂二氧化硅的连续层的外部部分，以使所选湿法蚀刻化学品具有比所述连续层的内部更高的蚀刻速率。常见的接触开口被各向异性地干蚀刻到包含未掺杂的二氧化硅的层中，并且在节点位置上进入到包含掺杂的二氧化硅的层中以向外暴露出节点位置。在该蚀刻之后，在公共接触开口内进行随之选择的化学反应的湿式蚀刻，以加宽包含未掺杂的二氧化硅的层的外部部分中的接触开口，与包含未掺杂的二氧化硅的层的内部相比较。选择并进行随后的湿式蚀刻以有效地选择性地基本上不横向蚀刻包含掺杂二氧化硅的层。

28. 发明授权

US5723382A Method of making a low-resistance contact to silicon having a titanium silicide interface, an amorphous titanium nitride barrier layer and a conductive plug 失效
标题翻译：对具有钛硅化物界面的硅进行低电阻接触的方法，非晶氮化钛阻挡层和导电插塞
公开(公告)号：US5723382A
公开(公告)日：1998-03-03
申请号：US509708
申请日：1995-07-31
申请人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
发明人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
IPC分类号： C23C16/34 , H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76855 , C23C16/34 , H01L21/28568 , H01L21/76843
摘要： This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe.sub.2).sub.4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon, or of metal, such as tungsten, follows, and proceeds until the contact opening is completely filled with either polycrystalline silicon or metal.
摘要翻译：本发明构成了采用利用四 - 二烷基酰胺基钛，Ti（NMe 2）4作为前体的低压化学气相沉积（LPCVD）形成的无定形氮化钛阻挡层的接触结构。通过将通过电介质层的接触开口蚀刻到要进行电接触的扩散区域来制造接触结构。钛金属沉积在晶片的表面上，使得扩散区域的暴露表面完全被金属层覆盖。钛金属层的至少一部分最终被转化为硅化钛，从而在扩散区的表面提供优异的导电界面。然后使用LPCVD工艺沉积氮化钛阻挡层，涂覆接触开口的壁和底板。多晶硅或金属如钨的化学气相沉积随后进行，直到接触开口完全充满多晶硅或金属。

29. 再颁专利

USRE35420E Method of increasing capacitance by surface roughening in semiconductor wafer processing 失效
标题翻译：通过半导体晶片加工中的表面粗糙度增加电容的方法
公开(公告)号：USRE35420E
公开(公告)日：1997-01-07
申请号：US491627
申请日：1995-06-19
申请人： David A. Cathey , Mark E. Tuttle , Tyler A. Lowrey
发明人： David A. Cathey , Mark E. Tuttle , Tyler A. Lowrey
IPC分类号： H01L21/02 , H01L21/334 , H01C21/28
CPC分类号： H01L28/84 , H01L29/66181
摘要： A method of increasing capacitance by surface roughening in semiconductor wafer processing includes the following steps: a) applying a first layer of material atop a substrate thereby defining an exposed surface; b) incontinuously adhering discrete solid particles to the first layer exposed surface to roughen the exposed surface; and c) applying a second layer of material atop the first layer and adhered solid particles to define an outer surface, the particles adhered to the first layer reducing roughness into the outer surface thereby increasing its surface area and accordingly capacitance of the second layer in the final wafer structure.
摘要翻译：通过在半导体晶片处理中通过表面粗糙度增加电容的方法包括以下步骤：a）在基板顶部施加第一层材料，从而限定暴露的表面; b）不连续地将离散的固体颗粒粘附到第一层暴露表面以使暴露的表面粗糙; 以及c）在第一层顶部施加第二层材料并粘附固体颗粒以限定外表面，所述粘附到第一层的颗粒将粗糙度减小到外表面中，从而增加其表面积，从而增加其中的第二层的电容最终的晶圆结构。

30. 发明授权

US5581104A Static discharge circuit having low breakdown voltage bipolar clamp 失效
标题翻译：静态放电电路具有低击穿电压双极钳位
公开(公告)号：US5581104A
公开(公告)日：1996-12-03
申请号：US425678
申请日：1995-04-18
申请人： Tyler A. Lowrey , Randal W. Chance
发明人： Tyler A. Lowrey , Randal W. Chance
IPC分类号： G06F15/78 , H01L21/822 , H01L27/02 , H01L27/04 , H01L27/06 , H01L29/78 , H01L23/62
CPC分类号： H01L29/0626 , H01L27/0251 , H01L29/861 , H01L2924/0002
摘要： A bipolar transistor and a bipolar diode are provided at an input pad on an integrated circuit, in order to shunt potential surges caused by electrostatic discharge (ESD). The approach makes use of a bipolar and a diode clamp with an optimized reverse biased breakdown from collector to base to shunt excess current away from sensitive regions with even current distribution for minimal damage. In order to improve the ESD immunity of the positive going ESD with respect to V.sub.SS, the reverse bias breakdowns of the diode and of the transistor's functioning as a collector/base diode are reduced. This circuit provides a simple low cost approach for improving ESD protection, in a process which fits into most standard Cmos process flows with few or no added process steps.
摘要翻译：在集成电路的输入焊盘上设置双极晶体管和双极二极管，以便分流由静电放电（ESD）引起的电涌。该方法利用双极和二极管钳位，具有从集电极到基极的优化的反向偏置击穿，以将过电流从具有均匀电流分布的敏感区域分流，以实现最小的损坏。为了提高正向ESD相对于VSS的ESD抗扰性，二极管和作为集电极/基极二极管的晶体管的反向偏压故障降低。该电路提供了一种简单的低成本方法来改善ESD保护，在一个适合大多数标准Cmos工艺流程的过程中，几乎没有或没有附加的工艺步骤。

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