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    • 21. 发明申请
    • Projection lens apparatus and rear projection type image display apparatus
    • 投影透镜装置和背投型图像显示装置
    • US20050259228A1
    • 2005-11-24
    • US11060251
    • 2005-02-18
    • Yuriko InadachiShuji KatoHidehiro IkedaNaoyuki OguraKoji Hirata
    • Yuriko InadachiShuji KatoHidehiro IkedaNaoyuki OguraKoji Hirata
    • G02B13/16G02B13/18G03B21/00G03B21/10G03B21/20G03B21/22
    • G02B13/16G02B13/18G03B21/10G03B21/20
    • For a projection lens apparatus having a six-group structure that enlarges and projects an image displayed on a projection tube, an appropriate distance is maintained between a power lens and an aspherical lens group that is located near a power lens on the image generation source side, and physical interference with the power lens is eliminated, so that productivity is increased while a cost reduction is achieved. A meniscus lens that has a concave face directed toward a screen and has a refracting power is employed as an aberration correction lens (fourth group lens 4) that is located near the power lens (third group lens 3) on the image generation source side. Further, the lens surface of the meniscus lens on the screen side has an aspherical shape, so that a curvature is increased from the light axis to a predetermined point located between the light axis and the outer edge, and is reduced from the predetermined point to the outer edge. Furthermore, an inexpensive low refractive index material that has an Abbe number (νd) of 57 or higher and a refractive index (nd) of 1.500 or lower and that has superior flowability is employed as the base material for the fourth group lens that is located nearest the glass power lens on the image generation source side.
    • 对于具有六组结构的投影透镜装置,其放大并投影显示在投影管上的图像,在功率透镜和位于图像生成源侧的功率透镜附近的非球面透镜组之间保持适当的距离 并且消除了与功率透镜的物理干扰,从而在实现成本降低的同时提高了生产率。 使用具有朝向屏幕的凹面并具有折射光焦度的弯月形透镜作为位于图像产生源侧的功率透镜(第三组透镜3)附近的像差校正透镜(第四组透镜4)。 此外,屏幕侧的弯月透镜的透镜表面具有非球面形状,使得曲率从光轴增加到位于光轴和外边缘之间的预定点,并且从预定点减小到 外边缘。 此外,使用阿贝数(nud)为57以上且折射率(nd)为1.500以下且具有优异的流动性的便宜的低折射率材料作为位于第四组透镜的基材 最靠近图像生成源侧的玻璃功率透镜。
    • 23. 发明申请
    • Associative memory and its retrieving method and router and network system
    • 关联内存及其检索方法以及路由器和网络系统
    • US20050047257A1
    • 2005-03-03
    • US10497570
    • 2001-12-10
    • Naoyuki Ogura
    • Naoyuki Ogura
    • G06F17/30G11C15/00G11C15/04H04L12/46G11C8/02
    • H04L45/00G11C15/00G11C15/04H04L45/742
    • An associative memory 4 for primary searching operation of an associative memory 23 supplies a valid state to a primary match line 13 corresponding to storage data coincident with search data 10 taking mask information into account, and supplies a value obtained from a result of a logical sum operation (an OR operation), with a valid state for the storage data as true, of all said coincident storage data to a counting means 25 as intermediate data 15. The counting means 25 supplies a result of an operation to the intermediate data 15 for counting the number of bits in an invalid state for the storage data to an associative memory 3 for secondary searching operations as secondary search data 19. Among secondary storage data obtained by carrying out said operation to said storage data, the associative memory 3 for secondary searching operation supplies a result of carrying out the searching operation of the secondary search data 19 to a secondary match line 21. The invalidation means 22 changes a secondary match line 21 corresponding to a primary match line 13 in an invalid state into an invalid state to supply to an external source as a match line 11.
    • 用于关联存储器23的主要搜索操作的关联存储器4将对应于与搜索数据10重合的存储数据相对应的主要匹配线13的有效状态提供给考虑了掩码信息,并且提供从逻辑和的结果获得的值 将所有所述重合的存储数据的存储数据的有效状态的操作(或操作)作为中间数据15输入到计数装置25.计数装置25将中间数据15的操作结果提供给中间数据15 将用于存储数据的无效状态的比特数计数到用于辅助搜索操作的关联存储器3作为辅助搜索数据19.在通过对所述存储数据执行所述操作而获得的辅助存储数据中,辅助搜索的关联存储器3 操作将辅助搜索数据19的搜索操作的结果提供给辅匹配线21.无效装置22 将处于无效状态的与主要匹配线13相对应的次要匹配线21改变为无效状态,以将其作为匹配线11提供给外部源。
    • 26. 发明授权
    • Non-volatile semiconductor device with an electrically erasable and
programmable read only memory showing an extremely high speed batch
erasure operation
    • 具有电可擦除和可编程只读存储器的非易失性半导体器件,显示出极高速的批量擦除操作
    • US5600595A
    • 1997-02-04
    • US526907
    • 1995-09-12
    • Naoyuki Ogura
    • Naoyuki Ogura
    • G11C17/00G11C16/02G11C16/16G11C16/34G11C13/00
    • G11C16/3445G11C16/16G11C16/344
    • A non-volatile semiconductor memory with an electrically erasable and programmable read only memory showing a high speed batch erasure operation is provided wherein applications of erasure pulse signals onto the memory cells are continued until the number of times of the erasure pulse signal applications made corresponds to a predetermined number already set before commencement of the erasure pulse signal applications, the predetermined number being set to correspond to an estimated number of times of the erasure pulse signal applications necessary for completing the batch erasure operation for subsequently repeating a set of an additional erasure pulse signal application onto the memory cells and a verifying process for verifying erasure states of all the memory cells until there is verified the fact that all the memory cells have been in erasure states.
    • 提供具有电可擦除和可编程只读存储器的非易失性半导体存储器,其显示高速批量擦除操作,其中擦除脉冲信号到存储器单元上的应用将持续直到擦除脉冲信号应用的次数对应于 在擦除脉冲信号应用开始之前已经设置的预定数量,预定数量被设置为对应于完成批量擦除操作所需的擦除脉冲信号应用的估计次数,用于随后重复一组附加擦除脉冲 信号应用到存储器单元上,以及用于验证所有存储单元的擦除状态的验证过程,直到验证了所有存储器单元已经处于擦除状态的事实。
    • 27. 发明授权
    • Equalizing mechanism in home-positioning apparatus
    • 家庭定位装置的均衡机制
    • US5563485A
    • 1996-10-08
    • US377158
    • 1995-01-24
    • Naoyuki Ogura
    • Naoyuki Ogura
    • G12B5/00B23Q1/26F16H19/06H05K13/00
    • B23Q1/267F16H19/06F16H2019/0668
    • The equalizing mechanism includes: timing belts laid in parallel to the rails for moving on a base; timing pulleys engaged with the timing belts; timing pulleys for interlocking mounted on shafts of the timing pulleys; and a timing belt for interlocking racked between the timing pulleys for interlocking whereby, when the movable beam on the rails for moving is driven, a driving force given by the rotation between the timing belt and the timing pulley on one side is equalized to be transmitted to the timing belt and the timing pulley on the other side through the timing pulley for interlocking, the timing belt for interlocking and the timing pulley for interlocking.
    • 均衡机构包括:平行于轨道平行放置在基座上的同步带; 正时皮带轮与正时皮带接合; 定时滑轮用于互锁安装在定时滑轮的轴上; 以及用于互锁的正时皮带,用于互锁的定时皮带轮之间,由此当用于移动的轨道上的可移动光束被驱动时,由一侧的同步皮带和正时皮带轮之间的旋转给出的驱动力被均衡以被传输 通过正时皮带轮与同步皮带和同步皮带轮相互锁定,用于联锁的同步皮带和用于互锁的定时皮带轮。
    • 28. 发明授权
    • Exponentiation remainder operation circuit
    • 指数余数运算电路
    • US5479365A
    • 1995-12-26
    • US163992
    • 1993-12-07
    • Naoyuki Ogura
    • Naoyuki Ogura
    • G06F7/50G06F7/72G09C1/00G06F7/38
    • G06F7/723G06F7/72
    • An exponentiation remainder operation circuit includes a first exponentiation remainder operator for performing an exponentiation remainder operation for a n/2 bit length parameter, in which n is an even number, a second exponentiation remainder operator, a first adder/subtractor for performing addition and subtraction for a n/2 bit length parameter, a second adder/subtractor, and a central processing unit (CPU) for performing an exponentiation remainder operation for a n-bit length parameter by controlling the exponentiation remainder operation of the first exponentiation remainder operator for the upper n/2 bits of the n-bit length parameter, the exponentiation remainder operation of the second exponentiation remainder operator for the lower n/2 bits of the n-bit length parameter, and addition and subtraction of the results of operations of the first and second exponentiation remainder operators by the first and second adders/subtractors.
    • 一个求幂余数运算电路包括一个第一求幂余数运算符,用于对其中n为偶数的/ 2位长度参数执行求幂余数运算,第二求幂余数算子,第一加法器/减法器, 一个/ 2位长度参数,一个第二加法器/减法器和一个中央处理单元(CPU),用于通过控制上位n的第一乘幂余数运算符的乘幂余数运算来执行n比特长度参数的求幂余数运算 / 2比特的n比特长度参数,n比特长度参数的较低n / 2比特的第二求幂余数运算符的求幂余数运算,以及第一和第二比特运算结果的加法和减法 由第一和第二加法器/减法器求幂余数运算符。
    • 30. 发明授权
    • Associative memory having a mask function for use in a network device
    • 具有用于网络设备的掩码功能的关联存储器
    • US08082360B2
    • 2011-12-20
    • US12836792
    • 2010-07-15
    • Naoyuki Ogura
    • Naoyuki Ogura
    • G06F15/16
    • H04L45/00G11C15/00G11C15/04H04L45/742
    • An associative memory 4 for primary searching operation of an associative memory 23 supplies a valid state to a primary match line 13 corresponding to storage data coincident with search data 10 taking mask information into account, and supplies a value obtained from a result of a logical sum operation (an OR operation), with a valid state for the storage data as true, of all said coincident storage data to a counting means 25 as intermediate data 15. The counting means 25 supplies a result of an operation to the intermediate data 15 for counting the number of bits in an invalid state for the storage data to an associative memory 3 for secondary searching operations as secondary search data 19. Among secondary storage data obtained by carrying out said operation to said storage data, the associative memory 3 for secondary searching operation supplies a result of carrying out the searching operation of the secondary search data 19 to a secondary match line 21. The invalidation means 22 changes a secondary match line 21 corresponding to a primary match line 13 in an invalid state into an invalid state to supply to an external source as a match line 11.
    • 用于关联存储器23的主要搜索操作的关联存储器4将对应于与搜索数据10重合的存储数据相对应的主要匹配线13的有效状态提供给考虑了掩码信息,并且提供从逻辑和的结果获得的值 将所有所述重合的存储数据的存储数据的有效状态的操作(或操作)作为中间数据15输入到计数装置25.计数装置25将中间数据15的操作结果提供给中间数据15 将用于存储数据的无效状态的比特数计数到用于辅助搜索操作的关联存储器3作为辅助搜索数据19.在通过对所述存储数据执行所述操作而获得的辅助存储数据中,辅助搜索的关联存储器3 操作将辅助搜索数据19的搜索操作的结果提供给辅匹配线21.无效装置22 将处于无效状态的与主要匹配线13相对应的次要匹配线21改变为无效状态,以将其作为匹配线11提供给外部源。