专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5895741A Photomask, manufacture of photomask, formation of pattern, manufacture of semiconductor device, and mask pattern design system 失效
标题翻译：光掩模，光掩模的制造，图案的形成，半导体器件的制造和掩模图案设计系统
公开(公告)号：US5895741A
公开(公告)日：1999-04-20
申请号：US906162
申请日：1997-08-05
申请人： Norio Hasegawa , Tsuneo Terasawa , Hiroshi Fukuda , Katsuya Hayano , Akira Imai , Akemi Moniwa , Shinji Okazaki
发明人： Norio Hasegawa , Tsuneo Terasawa , Hiroshi Fukuda , Katsuya Hayano , Akira Imai , Akemi Moniwa , Shinji Okazaki
IPC分类号： G03F1/00 , G03F1/26 , G03F1/32 , G03F1/36 , G03F7/20 , G03F9/00
CPC分类号： G03F1/32 , G03F1/26 , G03F1/36 , G03F7/70283 , G03F7/70433
摘要： A photomask used for printing a mask pattern by projection optics, in which a main pattern formed of a transparent area is provided in a semitransparent area formed of a semitransparent film and a phase shifter, and the phase angles of light beams passing through respective areas are different from each other substantially by 180.degree.. The photomask is intended to prevent a reduction in a production yield due to a resolution failure of the photomask, and to prevent generation of an unnecessary projected image. In this photomask, a transparent auxiliary pattern having the same phase angle of light as that of the transparent area is disposed around a main pattern formed of the transparent area, and a distance D between the center or a desired center line of the main pattern and that of the auxiliary pattern satisfies the relationship of D=b.lambda./NAm , where NAm is a mask-side numerical aperture of a projection lens, .lambda. is a wavelength of exposure light, and is a coefficient in the range of 1.35
摘要翻译：用于通过投影光学器件印制掩模图案的光掩模，其中由透明区域形成的半透明区域设置在由半透明膜和移相器形成的半透明区域中，并且通过各个区域的光束的相位角为彼此相差180度。光掩模旨在防止由于光掩模的分辨率故障导致的产量降低，并且防止产生不必要的投影图像。在该光掩模中，具有与透明区域相同的相位相位角的透明辅助图案设置在由透明区域形成的主图案周围，并且主图案的中心或期望中心线之间的距离D和辅助图案的图案满足D =bλ/ NAm的关系，其中NAm是投影透镜的掩模侧数值孔径，λ是曝光光的波长，并且b是1.35的范围内的系数

22. 发明授权

US07911600B2 Apparatus and a method for inspection of a mask blank, a method for manufacturing a reflective exposure mask, a method for reflective exposure, and a method for manufacturing semiconductor integrated circuits 有权
标题翻译：用于检查掩模板的装置和方法，反射式曝光掩模的制造方法，反射曝光方法以及半导体集成电路的制造方法
公开(公告)号：US07911600B2
公开(公告)日：2011-03-22
申请号：US12241614
申请日：2008-09-30
申请人： Tsuneo Terasawa , Toshihiko Tanaka , Tatsuya Aota
发明人： Tsuneo Terasawa , Toshihiko Tanaka , Tatsuya Aota
IPC分类号： G01N21/00
CPC分类号： G03F1/84 , G01N21/47 , G01N21/956 , G01N2021/4711 , G01N2021/95676
摘要： The mask blank inspection apparatus is constituted of a stage for mounting a reflective mask blank thereon, a light source for generating inspection light, a mirror serving as an illuminating optics, an imaging optical system, a beam splitter, two two-dimensional array sensors, signal storage units, an image processing unit, a main control unit for controlling operation of the whole apparatus, the first sensor being located at a position which is displaced by a predetermined distance from the focal plane of a first light beam, the second sensor being located at a position which is displaced by a predetermined distance from the focal plane of a second light beam along a opposite direction, whereby accurately and conveniently inspecting presence/absence and types of defects in reflective mask blank.
摘要翻译：掩模毛坯检查装置由用于安装反射掩模坯料的台架，用于产生检查灯的光源，用作照明光学器件的镜子，成像光学系统，分束器，两个二维阵列传感器，信号存储单元，图像处理单元，用于控制整个设备的操作的主控制单元，第一传感器位于从第一光束的焦平面偏移预定距离的位置，第二传感器是位于沿相反方向从第二光束的焦平面偏移了预定距离的位置，由此准确地和方便地检查反射掩模板中的存在/不存在和类型的缺陷。

23. 发明授权

US08488866B2 Method of inspecting mask pattern and mask pattern inspection apparatus 有权
标题翻译：检查掩模图案和掩模图案检查装置的方法
公开(公告)号：US08488866B2
公开(公告)日：2013-07-16
申请号：US12708041
申请日：2010-02-18
申请人： Tsuneo Terasawa , Toshihiko Tanaka , Hiroyuki Shigemura , Hajime Aoyama , Osamu Suga
发明人： Tsuneo Terasawa , Toshihiko Tanaka , Hiroyuki Shigemura , Hajime Aoyama , Osamu Suga
IPC分类号： G06K9/00
CPC分类号： G01N21/9501 , B82Y10/00 , B82Y40/00 , G01N21/956 , G03F1/24 , G03F1/84 , G03F7/70941 , G06T7/0006 , G06T2207/30148
摘要： A inspection image data of the chip A is captured and the data representing the amount of correction of flare corresponded to the chip A is appropriately loaded from the map storage block. Next, a inspection image of the chip A′ is captured, and the data representing the amount of correction of flare corresponded to the chip A′ is loaded from the flare map storage block as the amount of shifting of the edge of the contour of the pattern. The amount of correction is converted, by a correction data generation block which is a correction data generator, into the amount of geometrical correction of pattern which provides correction data. In the comparison block, the images of the geometry of two chips are compared and corrected on the amount of correction of flare generated by a correction data generation block, to thereby judge whether defect is found or not.
摘要翻译：捕获芯片A的检查图像数据，并且从地图存储块适当地加载表示对应于芯片A的闪光的校正量的数据。接下来，捕获芯片A'的检查图像，并且表示与芯片A'相对应的闪光量的校正量的数据从闪光图存储块加载为轮廓的边缘的移位量模式。通过作为校正数据生成器的校正数据生成块将修正量转换为提供校正数据的图案的几何校正量。在比较块中，对由校正数据生成块生成的闪光的校正量进行比较和修正两个芯片的几何图像，从而判断是否存在缺陷。

24. 发明申请

US20110043811A1 MASK DEFECT MEASUREMENT METHOD, MASK QUALITY DETERMINATION METHOD, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：掩模缺陷测量方法，掩模质量测定方法和半导体器件的制造方法
公开(公告)号：US20110043811A1
公开(公告)日：2011-02-24
申请号：US12750396
申请日：2010-03-30
申请人： Takeshi Yamane , Tsuneo Terasawa , Toshihiko Tanaka
发明人： Takeshi Yamane , Tsuneo Terasawa , Toshihiko Tanaka
IPC分类号： G01N21/47 , G01N21/00
CPC分类号： G01N21/956 , G01N2021/8874 , G01N2021/95676 , G03F1/84
摘要： A method for measuring a shape of a phase defect existing on an exposure mask includes making inspection light incident on the mask, measuring the intensity of light scattered in an angular range in which the width of an scattering area on the phase defect can be predicted, calculating a radius of the phase defect based on the measured scattered light intensity, changing the angular range of scattered light to be measured, remeasuring scattered light intensity in the thus changed angular range, and calculating a scattering cross-sectional area based on the scattered light intensity obtained by remeasurement. A process of remeasuring the scattered light intensity and calculating the scattering cross-sectional area is repeatedly performed until the remeasured scattered light intensity is saturated and the shape of the phase defect is determined by using the calculated radius of the phase defect and each of the calculated scattering cross-sectional areas.
摘要翻译：用于测量存在于曝光掩模上的相位缺陷的形状的方法包括：使检测光入射到掩模上，测量在可预测相位缺陷上的散射面积的宽度的角度范围内散射的光的强度，基于所测量的散射光强度，改变要测量的散射光的角度范围来计算相位缺陷的半径，在如此改变的角度范围内重新测量散射光强度，以及基于散射光计算散射截面积通过重新测量获得的强度。重新进行重新测量散射光强度并计算散射横截面积的过程，直到重新测量的散射光强度饱和，并且通过使用计算出的相位缺陷的半径来确定相位缺陷的形状，散射横截面积。

25. 发明申请

US20070188743A1 Method and system of defect inspection for mask blank and method of manufacturing semiconductor device using the same 有权
标题翻译：掩模毛坯的缺陷检查方法和系统以及使用其的制造半导体器件的方法
公开(公告)号：US20070188743A1
公开(公告)日：2007-08-16
申请号：US11707127
申请日：2007-02-16
申请人： Toshihiko Tanaka , Tsuneo Terasawa , Yoshihiro Tezuka
发明人： Toshihiko Tanaka , Tsuneo Terasawa , Yoshihiro Tezuka
IPC分类号： G01N21/88 , G01N21/00
CPC分类号： G01N21/956 , B82Y10/00 , B82Y40/00 , G01N2021/8822 , G01N2021/95676 , G03F1/24 , G03F1/84
摘要： Defect detection is performed with two settings, that is, setting of a focus position where a signal intensity obtained from a dot pattern is maximum and setting of a focus position where a signal intensity obtained from a hole pattern is maximum. In addition, defect detection is performed at a predetermined focus position previously set and for the detected defect, the focus position is changed at that position to find a focus position where the signal intensity is maximum. If the focus position is away from a signal light-receiving system, the defect is determined as dot-shaped. If the focus position is close to the signal light-receiving system, the defect is determined as hole-shaped. If the focus position is intermediate of them, the defect is determined as an elongated-shaped.
摘要翻译：通过两种设置执行缺陷检测，即，从点图案获得的信号强度设置为最大的聚焦位置的设置和从孔图案获得的信号强度的最大焦点位置的设置。此外，在预先设定的预定焦点位置执行缺陷检测，对于检测到的缺陷，在该位置改变焦点位置以找到信号强度最大的聚焦位置。如果聚焦位置远离信号光接收系统，则该缺陷被确定为点状。如果聚焦位置靠近信号光接收系统，则将该缺陷确定为孔形。如果焦点位置是它们的中间位置，则将缺陷确定为细长形状。

26. 发明申请

US20080276215A1 Mask Pattern Designing Method Using Optical Proximity Correction in Optical Lithography, Designing Device, and Semiconductor Device Manufacturing Method Using the Same 审中-公开
标题翻译：光学平版印刷中的光学接近校正的掩模图案设计方法，设计装置和使用其的半导体器件制造方法
公开(公告)号：US20080276215A1
公开(公告)日：2008-11-06
申请号：US11910049
申请日：2006-03-28
申请人： Tetsuya Higuchi , Hirokazu Nosato , Masahiro Murakawa , Hidenori Sakanashi , Nobuyuki Yoshioka , Tsuneo Terasawa , Toshihiko Tanaka
发明人： Tetsuya Higuchi , Hirokazu Nosato , Masahiro Murakawa , Hidenori Sakanashi , Nobuyuki Yoshioka , Tsuneo Terasawa , Toshihiko Tanaka
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G03F1/36 , G06N3/126
摘要： A method for designing a mask pattern realizes shortening the ever-growing time for the OPC treatment, decreases the fabrication TAT of a semiconductor device and cuts cost. A method for fabricating a semiconductor device uses the mask pattern designed. This invention performs the OPC treatment in advance on a cell library constituting the basic configuration of a semiconductor circuit pattern and prepares a semiconductor chip using the cell library that has undergone the OPC treatment. The method for designing a mask pattern includes the steps of designing a cell library pattern by executing for each of the cell libraries a treatment for correcting proximity effect directed to correcting the change of shape taking place during the formation of a pattern by the exposure of a mask pattern, designing a mask pattern by laying out the cell libraries and changing the amount of correction of proximity effect applied to the cell libraries in consideration of the influence of the cell library patterns disposed peripherally. This treatment for correction is executed by the degree of influence exerted by surrounding patterns collected in advance and the genetic algorithm.
摘要翻译：用于设计掩模图案的方法实现缩短OPC处理的不断增长的时间，减少半导体器件的制造TAT并降低成本。半导体器件的制造方法使用设计的掩模图案。本发明预先在构成半导体电路图案的基本结构的单元库中进行OPC处理，并且使用已经经过OPC处理的单元库来制备半导体芯片。用于设计掩模图案的方法包括以下步骤：通过针对每个单元库执行用于修正邻近效应的处理的设计单元库模式的步骤，所述处理用于校正在形成模式期间发生的形状变化掩模图案，考虑到周边设置的细胞库图案的影响，通过铺设细胞库并改变施加到细胞库的邻近效应的校正量来设计掩模图案。这种校正处理是通过预先收集的周围图案和遗传算法的影响程度来执行的。

27. 发明申请

US20070074146A1 Method for designing mask pattern and method for manufacturing semiconductor device 审中-公开
标题翻译：设计掩模图案的方法和制造半导体器件的方法
公开(公告)号：US20070074146A1
公开(公告)日：2007-03-29
申请号：US11526783
申请日：2006-09-26
申请人： Toshihiko Tanaka , Osamu Suga , Tsuneo Terasawa , Tetsuya Higuchi , Hidenori Sakanashi , Hirokazu Nosato , Tetsuaki Matsunawa
发明人： Toshihiko Tanaka , Osamu Suga , Tsuneo Terasawa , Tetsuya Higuchi , Hidenori Sakanashi , Hirokazu Nosato , Tetsuaki Matsunawa
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A semiconductor chip is manufactured using a cell library pattern obtained by performing OPC (optical proximity correction) process at the time of a cell single arrangement to a cell library pattern which forms a basic structure of a semiconductor circuit pattern in advance. A plurality of cell libraries are arranged to design a mask pattern and a correction amount of OPC performed to the cell libraries is changed with taking into account the influence of a pattern of cell libraries arranged around a target cell. Further, a cell group with the same arrangement of surrounding cells including the target cell is extracted and is registered as a cell set, and a cell set with the same cell arrangement as that of the registered cell set is produced by copying without re-calculating OPC inside the cell set.
摘要翻译：使用通过在单元格单元配置时对预先形成半导体电路图案的基本结构的单元库图案执行OPC（光学邻近校正）处理而获得的单元库模式来制造半导体芯片。布置多个单元库以设计掩模图案，并且考虑到布置在目标单元周围的单元库的图案的影响，改变对单元库执行的OPC的校正量。此外，提取具有包括目标单元的周围单元的相同排列的单元组，并将其注册为单元组，并且通过复制产生具有与注册单元组相同单元布置的单元组，而不重新计算 OPC内部的单元格集。

28. 发明授权

US08384888B2 Mask defect measurement method, mask quality determination and method, and manufacturing method of semiconductor device 有权
标题翻译：掩模缺陷测量方法，掩模质量测定和方法以及半导体器件的制造方法
公开(公告)号：US08384888B2
公开(公告)日：2013-02-26
申请号：US12750396
申请日：2010-03-30
申请人： Takeshi Yamane , Tsuneo Terasawa , Toshihiko Tanaka
发明人： Takeshi Yamane , Tsuneo Terasawa , Toshihiko Tanaka
IPC分类号： G01N21/00
CPC分类号： G01N21/956 , G01N2021/8874 , G01N2021/95676 , G03F1/84
摘要： A method for measuring a shape of a phase defect existing on an exposure mask includes making inspection light incident on the mask, measuring the intensity of light scattered in an angular range in which the width of an scattering area on the phase defect can be predicted, calculating a radius of the phase defect based on the measured scattered light intensity, changing the angular range of scattered light to be measured, remeasuring scattered light intensity in the thus changed angular range, and calculating a scattering cross-sectional area based on the scattered light intensity obtained by remeasurement. A process of remeasuring the scattered light intensity and calculating the scattering cross-sectional area is repeatedly performed until the remeasured scattered light intensity is saturated and the shape of the phase defect is determined by using the calculated radius of the phase defect and each of the calculated scattering cross-sectional areas.
摘要翻译：用于测量存在于曝光掩模上的相位缺陷的形状的方法包括：使检测光入射到掩模上，测量在可预测相位缺陷上的散射面积的宽度的角度范围内散射的光的强度，基于所测量的散射光强度，改变要测量的散射光的角度范围来计算相位缺陷的半径，在如此改变的角度范围内重新测量散射光强度，以及基于散射光计算散射截面积通过重新测量获得的强度。重新进行重新测量散射光强度和计算散射截面面积的过程，直到重新测量的散射光强度饱和，并且通过使用计算出的相缺陷的半径来确定相缺陷的形状，散射横截面积。

29. 发明授权

US07630068B2 Method and system of defect inspection for mask blank and method of manufacturing semiconductor device using the same 有权
标题翻译：掩模毛坯的缺陷检查方法和系统以及使用其的制造半导体器件的方法
公开(公告)号：US07630068B2
公开(公告)日：2009-12-08
申请号：US11707127
申请日：2007-02-16
申请人： Toshihiko Tanaka , Tsuneo Terasawa , Yoshihiro Tezuka
发明人： Toshihiko Tanaka , Tsuneo Terasawa , Yoshihiro Tezuka
IPC分类号： G01N21/88 , G01N21/00
CPC分类号： G01N21/956 , B82Y10/00 , B82Y40/00 , G01N2021/8822 , G01N2021/95676 , G03F1/24 , G03F1/84
摘要： Defect detection is performed with two settings, that is, setting of a focus position where a signal intensity obtained from a dot pattern is maximum and setting of a focus position where a signal intensity obtained from a hole pattern is maximum. In addition, defect detection is performed at a predetermined focus position previously set and for the detected defect, the focus position is changed at that position to find a focus position where the signal intensity is maximum. If the focus position is away from a signal light-receiving system, the defect is determined as dot-shaped. If the focus position is close to the signal light-receiving system, the defect is determined as hole-shaped. If the focus position is intermediate of them, the defect is determined as an elongated-shaped.
摘要翻译：通过两种设置执行缺陷检测，即，从点图案获得的信号强度设置为最大的聚焦位置的设置和从孔图案获得的信号强度的最大焦点位置的设置。此外，在预先设定的预定焦点位置执行缺陷检测，对于检测到的缺陷，在该位置改变焦点位置以找到信号强度最大的聚焦位置。如果聚焦位置远离信号光接收系统，则该缺陷被确定为点状。如果聚焦位置靠近信号光接收系统，则将该缺陷确定为孔形。如果焦点位置是它们的中间位置，则将缺陷确定为细长形状。

30. 发明申请

US20080250383A1 Method for designing mask pattern and method for manufacturing semiconductor device 审中-公开
标题翻译：设计掩模图案的方法和制造半导体器件的方法
公开(公告)号：US20080250383A1
公开(公告)日：2008-10-09
申请号：US11526820
申请日：2006-09-26
申请人： Toshihiko Tanaka , Tsuneo Terasawa , Nobuyuki Yoshioka , Tetsuya Higuchi , Hidenori Sakanashi , Hirokazu Nosato , Masahiro Murakawa
发明人： Toshihiko Tanaka , Tsuneo Terasawa , Nobuyuki Yoshioka , Tetsuya Higuchi , Hidenori Sakanashi , Hirokazu Nosato , Masahiro Murakawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/08
摘要： A mask pattern designing method capable of achieving the reduction in the increasing OPC processing time, shortening the manufacture TAT of a semiconductor device, and achieving the cost reduction is provided. An OPC (optical proximity correction) process at the time when a cell is singularly arranged is performed to a cell library pattern which forms a basic structure of a semiconductor circuit pattern in advance, and a semiconductor chip is produced using the cell library pattern to which the OPC process has been performed. At this time, since the cell library pattern which has been OPC-processed in advance is influenced by the cell library patterns around it, the correction process thereof is performed to the end portions of the patterns near the cell boundary. As particularly effective OPC correction means, the genetic algorithm is used.
摘要翻译：提供了能够实现OPC处理时间的增加减少，缩短半导体器件的制造TAT以及实现成本降低的掩模图案设计方法。对单元格单独排列时的OPC（光学邻近校正）处理进行预先对形成半导体电路图案的基本结构的单元库模式，并使用单元库模式生成半导体芯片，已经执行了OPC过程。此时，由于预先对其进行了OPC处理的单元库模式受其周围的单元库模式的影响，所以对单元边界附近的图案的端部进行修正处理。作为特别有效的OPC校正手段，使用遗传算法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式