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21. 发明授权

US08331151B2 Semiconductor memory including control unit responsive to erase command to determine selection of redundant memory block 有权
标题翻译：半导体存储器包括响应于擦除命令的控制单元，以确定冗余存储块的选择
公开(公告)号：US08331151B2
公开(公告)日：2012-12-11
申请号：US12965951
申请日：2010-12-13
申请人： Naoaki Sudo
发明人： Naoaki Sudo
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C29/84 , G06F11/1048 , G11C2029/0411
摘要： A semiconductor memory device includes a memory region including memory cells configured to store data, a redundant region including memory cells configured to store data, and a control unit. The control unit is responsive to an erase command to execute, prior to an erase operation corresponding to the erase command, an error detection operation on data read from the memory region to detect whether the memory region is a defective memory region to be replaced by the redundant region.
摘要翻译：一种半导体存储器件包括存储区域，该存储器区域包括被配置为存储数据的存储单元，包括被配置为存储数据的存储器单元的冗余区域和控制单元。控制单元响应于擦除命令，在与擦除命令相对应的擦除操作之前执行对从存储器区域读取的数据的错误检测操作，以检测存储器区域是否将被替换的缺陷存储器区域冗余区域。

22. 发明授权

US07733728B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07733728B2
公开(公告)日：2010-06-08
申请号：US11442296
申请日：2006-05-30
申请人： Naoaki Sudo
发明人： Naoaki Sudo
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： Disclosed is to enable high speed reading from a storage node when a read is executed. A main cell array is constituted from main cell division units 20a. Each main cell division unit 20a includes select gates SG that extend in a vertical direction, common sources CS that extend in a horizontal direction below the select gates SG outside a cell region, word lines W0 to W15 that extend above the select gates SG in the horizontal direction within the cell region, a plurality of storage nodes disposed in the vicinity of intersecting portions between the word lines W0 to W15 and the select gates SG, respectively, below the word lines W0 to W15, and a bit line MGB for transmitting to a sense amplifier 11 information on one of the storage nodes through a selection switch 21. In the main cell division unit 20a, an inversion layer is formed below each of the select gates SG within the cell region by applying a positive voltage to each of the select gates SG. A reference cell array is constituted from a reference cell division unit 30a having a same configuration as the main cell division unit 20a.
摘要翻译：公开了当执行读取时能够从存储节点进行高速读取。主单元阵列由主单元分割单元20a构成。每个主单元分割单元20a包括在垂直方向上延伸的选择栅极SG，在单元区域外部的选择栅极SG下方沿水平方向延伸的公共源CS，在选择栅极SG上方延伸的字线W0至W15 在单元区域内的水平方向，分别设置在字线W0〜W15和选择栅极SG之间的交叉部分附近的多个存储节点，位于字线W0〜W15的下方，以及位线MGB，用于发送到一个读出放大器11通过选择开关21在一个存储节点上的信息。在主单元划分单元20a中，通过向单元区域内的每个选择栅极SG施加正电压选择门SG。参考单元阵列由具有与主单元分割单元20a相同配置的参考单元划分单元30a构成。

23. 发明申请

US20070045715A1 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US20070045715A1
公开(公告)日：2007-03-01
申请号：US11510618
申请日：2006-08-28
申请人： Naoaki Sudo , Kohji Kanamori , Kazuhiko Sanada
发明人： Naoaki Sudo , Kohji Kanamori , Kazuhiko Sanada
IPC分类号： H01L29/788
CPC分类号： H01L29/7885 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A semiconductor storage device in which product cost is reduced includes a memory cell section (cells belonging to word lines) and a bypass section (cells belonging to bypass word lines). The memory cell section has a select gate, floating gates, a first diffusion region, a second diffusion region and a first control gate. The bypass section has the first select gate, the first diffusion region, the second diffusion region and a second control gate. The second control gate controls a channel in an area between the select gate and the first diffusion region or between the select gate and the second diffusion region. The channel of the bypass section becomes a current supply path when a cell of the memory cell section is read out.
摘要翻译：产品成本降低的半导体存储装置包括存储单元部分（属于字线的单元）和旁路部分（属于旁路字线的单元）。存储单元部分具有选择栅极，浮置栅极，第一扩散区域，第二扩散区域和第一控制栅极。旁路部分具有第一选择栅极，第一扩散区域，第二扩散区域和第二控制栅极。第二控制栅极控制选择栅极和第一扩散区域之间或选择栅极和第二扩散区域之间的区域中的沟道。当读出存储单元部分的单元时，旁通部分的通道变为电流供应路径。

24. 发明申请

US20060289922A1 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060289922A1
公开(公告)日：2006-12-28
申请号：US11453796
申请日：2006-06-16
申请人： Naoaki Sudo , Kohji Kanamori
发明人： Naoaki Sudo , Kohji Kanamori
IPC分类号： H01L29/76
CPC分类号： H01L29/7887 , G11C16/0441 , G11C16/0491 , G11C16/28 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： To achieve a high-speed and reliable read operation. A unit cell is constituted by a select gate 3 provided in a first region and on a substrate 1 with an insulating film 2 interposed inbetween, a floating gate 6a provided in a second region adjacent to the first region with an insulating film 5 interposed inbetween, a diffusion region 7a provided in a third region adjacent to the second region and on the surface of the substrate, and a control gate 11 provided on the top of the floating gate 6a with an insulating film 8 interposed inbetween. Each data bit is stored using corresponding first unit cell and second unit cell.
摘要翻译：实现高速可靠的读取操作。单位电池由设置在第一区域中的选择栅极3和介于其间的绝缘膜2的基板1构成，设置在与第一区域相邻的第二区域中的浮置栅极6a与介于其间的绝缘膜5 设置在与第二区域相邻的第三区域和衬底的表面上的扩散区域7a，以及设置在浮置栅极6a的顶部上的绝缘膜8的控制栅极11。使用对应的第一单元单元和第二单元单元存储每个数据位。

25. 发明授权

US06400601B1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06400601B1
公开(公告)日：2002-06-04
申请号：US09602178
申请日：2000-06-22
申请人： Naoaki Sudo , Satoshi Katagiri
发明人： Naoaki Sudo , Satoshi Katagiri
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C16/3454 , G11C2211/5621
摘要： A nonvolatile semiconductor device is provided, which does not need excessive writing or verification operations, except for the originally required writing and verification operations. The data is arranged in the order from the lowest “11”, “10”, “01”, to the highest “01”. Four valued writing data are set in the latches 1 and 2 by data signals DL1 and DL2, and the latch 3 is initialized to “0”. Writing is executed by three stages, and before writing at each stage, if the latch 3 is “0”, the data is transferred to the latch 2. Writing is only executed when any one latch is “0”, and the latch is changed to “1” after the verification is completed. First, writing is executed up to the threshold value of the data “01”, except the data “11” where the latch 2 is “0”. Next, writing is executed for the data “00” and “01” up to the threshold value of the data “00”, where the latch 1 is “0”. Finally, the data “01” where the latch 2 is “0” is written up to the threshold value of “01”.
摘要翻译：提供了不需要过多的写入或验证操作的非易失性半导体器件，除了最初要求的写入和验证操作。数据按照从最低“11”，“10”，“01”到最高“01”的顺序排列。通过数据信号DL1和DL2在锁存器1和2中设置四值写入数据，并且锁存器3被初始化为“0”。写入由三个阶段执行，并且在每个阶段写入之前，如果锁存器3为“0”，则数据被传送到锁存器2.写入仅在任何一个锁存器为“0”且锁存器被改变时才执行到验证完成后为“1”。首先，除了锁存器2为“0”的数据“11”之外，执行直到数据“01”的阈值的写入。接下来，对数据“00”和“01”执行写入，直到数据“00”的阈值为止，其中锁存器1为“0”。最后，将锁存器2为“0”的数据“01”写入阈值“01”。

26. 发明授权

US06320455B1 Boost circuit 有权
标题翻译：升压电路
公开(公告)号：US06320455B1
公开(公告)日：2001-11-20
申请号：US09533176
申请日：2000-03-22
申请人： Naoaki Sudo
发明人： Naoaki Sudo
IPC分类号： G05F110
CPC分类号： G11C16/30 , H02M3/07 , H02M2003/077
摘要： Boost circuit units are connected in parallel. A boost output voltage VBOOST′ of a dummy boost circuit unit having the same configuration as the boost circuit units is detected by a voltage detection circuit. The voltage detection circuit outputs a signal TBST2 which becomes “high” when VBOOST′ is lower than VLIMIT and “low” when VBOOST′ is equal to or higher than VLIMIT. The TBST2 signal is input to a NAND circuit. When a “high” signal is input to the NAND circuit, an input voltage ATDBST2 is input to the boost circuit unit as well via the NAND circuit and the two boost circuit units perform boost operation. Thus, a boost circuit can suppress the dispersion of the boost voltage caused by the dispersion of the process condition and the variation of the external temperature besides the variation of the power supply voltage Vcc.
摘要翻译：升压电路单元并联连接。具有与升压电路单元相同配置的虚拟升压电路单元的升压输出电压VBOOST'由电压检测电路检测。当VBOOST'低于VLIMIT时，电压检测电路输出变为“高”的信号TBST2，当VBOOST'等于或高于VLIMIT时，输出“低”。 TBST2信号输入到NAND电路。当“高”信号输入到NAND电路时，输入电压ATDBST2也经由NAND电路输入到升压电路单元，两个升压电路单元进行升压操作。因此，除了电源电压Vcc的变化之外，升压电路可以抑制由处理条件的分散引起的升压电压的偏差和外部温度的变化。

27. 发明授权

US06215352B1 Reference voltage generating circuit with MOS transistors having a floating gate 有权
标题翻译：具有浮置栅极的MOS晶体管的基准电压发生电路
公开(公告)号：US06215352B1
公开(公告)日：2001-04-10
申请号：US09236331
申请日：1999-01-25
申请人： Naoaki Sudo
发明人： Naoaki Sudo
IPC分类号： G05F110
CPC分类号： G05F3/242
摘要： A reference voltage generating circuit with MOS transistors having a floating gate is disclosed. The reference voltage generating circuit has first and second MOS transistors in which substantially the same current flows by means of a current mirror circuit. The differential voltage between the threshold voltages of the first and second MOS transistors is applied from the source of the first transistor as the reference voltage. The first and second transistors are of a construction that includes a floating gate, and the threshold voltage can be set to any value by means of the amount of charge injected to the floating gate.
摘要翻译：公开了具有浮置栅极的MOS晶体管的参考电压发生电路。参考电压产生电路具有第一和第二MOS晶体管，其中基本上相同的电流通过电流镜电路流动。从第一晶体管的源极施加第一和第二MOS晶体管的阈值电压之间的差分电压作为参考电压。第一和第二晶体管是包括浮置栅极的结构，并且阈值电压可以通过注入到浮动栅极的电荷量来设置为任何值。

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