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21. 发明授权

US5768190A Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller 失效
标题翻译：具有自动写入验证控制器的电可擦除和可编程的非易失性半导体存储器
公开(公告)号：US5768190A
公开(公告)日：1998-06-16
申请号：US749935
申请日：1996-11-14
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
IPC分类号： G11C16/10 , G11C16/12 , G11C16/26 , G11C16/34 , G11C16/02
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/3454
摘要： A NAND-cell type EEPROM having an array of memory cells connected to bit lines. Each cell includes one transistor with floating and control gate electrodes. Electrons are tunneled to or from the floating gate to write data. A sense/latch circuit is connected to the bit lines for selectively performing sense and latch operations of the write data. A program controller is provided for writing and verifying the data into a selected memory cell. Data is rewritten if a resultant threshold voltage in the selected memory cell of the written data is insufficient. A rewrite-data setting section is provided for performing a logic operation with respect to data read from the selected cell and write data being latched into the sense/latch circuit, and for automatically updating a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the memory being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier after being reset.
摘要翻译：具有连接到位线的存储器单元阵列的NAND单元型EEPROM。每个单元包括具有浮置和控制栅电极的一个晶体管。电子通过隧道传输到浮动栅极或从浮动栅极写入数据。感测/锁存电路连接到位线，用于选择性地执行写入数据的检测和锁存操作。提供了一种程序控制器，用于将数据写入和验证到选定的存储单元中。如果写入数据的选定存储单元中的合成阈值电压不足，则重写数据。提供重写数据设置部分，用于执行关于从所选择的单元读取的数据的逻辑操作和被锁存到感测/锁存电路中的写入数据，并且用于自动更新存储在感测/锁存电路中的重写数据，根据正在验证的存储器对每个位线进行操作。感测/锁存电路包括CMOS触发器电路，其在验证操作开始时用作数据锁存器，并且在复位之后用作读出放大器。

22. 发明授权

US5627782A Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller 失效
标题翻译：具有自动写入验证控制器的电可擦除和可编程的非易失性半导体存储器
公开(公告)号：US5627782A
公开(公告)日：1997-05-06
申请号：US473739
申请日：1995-06-07
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
IPC分类号： G11C16/10 , G11C16/12 , G11C16/26 , G11C16/34 , G11C16/02
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/3454
摘要： A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense/latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier once after it is reset.
摘要翻译： NAND单元型EEPROM包括连接到位线的存储单元的阵列。每个单元包括具有浮置栅极和控制栅极电极的一个晶体管，其中电子被隧道传输到浮动栅极或从浮动栅极传输到其中以写入数据。感测/锁存电路连接到位线，并且有选择地执行写数据的检测操作和锁存操作。提供了一种程序控制器，用于将数据写入指定区域中的所选择的存储单元中，并且用于读取写入所选单元格中的数据，以验证其合成阈值电压是否在允许范围内。如果不足，则重写数据。提供重写数据设置部分，用于对来自所选择的单元的读取数据进行逻辑运算，并将写入数据锁存在感测/锁存电路中，并且自动更新存储在感测/锁存器中的重写数据根据实际写入状态对每个位线进行电路验证。感测/锁存电路包括CMOS触发器电路，其在验证操作开始时用作数据锁存器，并且在复位之后用作读出放大器。

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