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21. 发明授权

US07130333B2 Method and device for frame sync detection using channel combining and correlation 有权
标题翻译：使用信道组合和相关的帧同步检测方法和装置
公开(公告)号：US07130333B2
公开(公告)日：2006-10-31
申请号：US09995095
申请日：2001-11-27
申请人： Leroy Andrew Gibson, Jr. , Dan M. Griffin , Lyman D. Horne , Randal R. Sylvester
发明人： Leroy Andrew Gibson, Jr. , Dan M. Griffin , Lyman D. Horne , Randal R. Sylvester
IPC分类号： H04B1/707
CPC分类号： H04B1/7075
摘要： A method and device for frame sync detection using signal combining and correlation. The method comprises the steps of despreading PN coded signals to provide in-phase I1–In, and quadrature phase Q1–Qn signals, wherein each I1–In and each Q1–Qn signal contains at least one sync bit and n≧2. The at least one sync bit from each I1–In, and quadrature phase Q1–Qn signals are summed to form sums Is1 and Qs1, respectively. The next step provides a reference sync having at least one bit and compares each sum Is1 and Qs1 with the at least one reference bit. The results of each Is1 and Qs1 comparison are accumulated so as to form two accumulates, IA and QA, respectively. Each accumulate IA and QA, is squared to form IA2 and QA2 from which the sum IA2 and QA2 is formed. The sum IA2+QA2 is compared with a predetermined threshold and as a result of the comparison a determination of whether frame sync has been achieved is made.
摘要翻译：一种使用信号组合和相关的帧同步检测的方法和装置。该方法包括以下步骤：对PN编码信号进行解扩，以提供同相I 1 -I N n N，以及正交相位Q 1 -Q 1，其中每个I 1 -I n个和每个Q 1 -Q N n个/ N个 >信号包含至少一个同步位，n> = 2。来自每个I 1 -I N SUB的至少一个同步位以及正交相位Q 1 -Q N n N 信号被相加以形成和分别分别为I S 1和S 2。下一步骤提供具有至少一个比特的参考同步，并将每个和I 1和S 1和S 1＆lt; S 1＆lt;和＆lt; S 1＆lt;＆gt;和至少一个参考比特进行比较。每个I＆lt; s1＆gt;和＆lt; s1＆lt;比较比较的结果被累积，以便形成两个累加， SUB>。每个累加I A和A A A均被平方以形成I A 2和Q A 2，总和2和/或2＆lt; 2＆gt;和＆lt; 2＆gt; 2＆lt; 2＆gt; 形成了。将总和与预定阈值进行比较，并作为比较的结果。确定是否已经实现帧同步。

22. 发明授权

US4121290A Analog sound velocity calculator 失效
标题翻译：模拟声速计算器
公开(公告)号：US4121290A
公开(公告)日：1978-10-17
申请号：US788371
申请日：1977-04-18
申请人： Royce Allen , Jerry L. Sutton , Dan M. Griffin , Hal W. Frye , Joseph G. Colborn
发明人： Royce Allen , Jerry L. Sutton , Dan M. Griffin , Hal W. Frye , Joseph G. Colborn
IPC分类号： G01H5/00 , G06G7/48 , G06G7/78 , H04B13/00
CPC分类号： G01H5/00 , G06G7/48
摘要： An analog apparatus for determining the velocity of sound at a selected position in a liquid media is provided with a means for representing the conductivity, temperature, and depth of the position in the form of analog voltages, and is further provided with an analog calculating means receiving each of the voltages for calculating the velocity of sound as a function of conductivity, temperature, and depth. The sound velocity may be calculated at a succession of positions to provide a sound velocity versus depth profile of the liquid media.
摘要翻译：用于确定液体介质中选定位置处的声速的模拟装置具有用于以模拟电压的形式表示位置的电导率，温度和深度的装置，还具有模拟计算装置接收用于计算作为电导率，温度和深度的函数的声速的每个电压。可以在连续的位置处计算声速，以提供液体介质的声速与深度分布。

23. 发明授权

US4118782A Digital sound velocity calculator 失效
标题翻译：数字声速计算器
公开(公告)号：US4118782A
公开(公告)日：1978-10-03
申请号：US780750
申请日：1977-03-24
申请人： Royce H. Allen , Jerry L. Sutton , Dan M. Griffin , Hal W. Frye , Joseph G. Colborn
发明人： Royce H. Allen , Jerry L. Sutton , Dan M. Griffin , Hal W. Frye , Joseph G. Colborn
IPC分类号： G01H5/00 , G01P3/00
CPC分类号： G01H5/00
摘要： A digital apparatus for determining the velocity of sound at a selected position in a liquid media is provided with a means for representing the conductivity, temperature and depth of the position in the form of digital numbers, and provides a digital calculating means receiving each of the digital numbers for calculating the velocity of sound as a function of conductivity, temperature, and depth. The sound velocity may be calculated at a succession of positions to provide sound velocity versus depth profile of the liquid media.
摘要翻译：用于确定在液体介质中的选定位置处的声速的数字装置设置有用于以数字数字的形式表示位置的电导率，温度和深度的装置，并且提供数字计算装置，用于计算声速作为电导率，温度和深度的函数的数字数字。可以在连续的位置处计算声速，以提供液体介质的声速与深度曲线。

24. 发明授权

US07164733B1 Method and device for compensating for digital data demodulation phase uncertainty 失效
标题翻译：用于补偿数字数据解调相位不确定度的方法和装置
公开(公告)号：US07164733B1
公开(公告)日：2007-01-16
申请号：US10273929
申请日：2002-10-17
申请人： Dan M. Griffin , Randal R. Sylvester
发明人： Dan M. Griffin , Randal R. Sylvester
IPC分类号： H04L27/00
CPC分类号： H04L27/227 , H04L2027/003 , H04L2027/0055 , H04L2027/0067
摘要： A method and system for compensating digital data demodulation phase uncertainty is provided. The method includes the steps of identifying a phase reference quadrant, the phase reference quadrant having a phase reference axis and four quadrants, I, II, III, and IV; receiving known digital data; and forming a phase vector from the known digital data, determining which quadrant the phase vector is located in and rotating the phase vector to the phase reference quadrant if it is determined that the phase vector is not located in the phase reference quadrant. The last step generates a phase error signal proportional to the resulting angle by rotating the phase vector −45° and measuring the resulting angle between the phase vector and the phase reference axis.
摘要翻译：提供了一种用于补偿数字数据解调相位不确定性的方法和系统。该方法包括以下步骤：识别相位参考象限，相位参考象限具有相位参考轴和四个象限I，II，III和IV; 接收已知的数字数据; 以及如果确定相位矢量不位于相位参考象限中，则从已知的数字数据形成相位矢量，确定相位矢量所在的象限，并将相位矢量旋转到相位参考象限。最后一步通过旋转相位矢量-45°并测量相位矢量和相位参考轴之间产生的角度，产生与所得到的角度成比例的相位误差信号。

25. 发明授权

US06285261B1 Digital clock recovery loop 有权
标题翻译：数字时钟恢复回路
公开(公告)号：US06285261B1
公开(公告)日：2001-09-04
申请号：US09610177
申请日：2000-07-05
申请人： George E. Pax , James E. O'Toole , Dan M. Griffin
发明人： George E. Pax , James E. O'Toole , Dan M. Griffin
IPC分类号： H03L100
CPC分类号： H03L7/0895 , H03L7/0896 , H03L7/113 , H04B1/707 , H04L7/033
摘要： A method of using a phase lock loop to receive an oscillating input signal and produce an output signal, the phase lock loop comprising a plurality of flip-flops which are chained together, the plurality of flip-flops including a first flip-flop having a first output, including a second flip-flop having an input coupled to the first output and having a second output, and including a third flip-flop having an input coupled to the second output, the phase lock loop further comprising a control node, the method including using the flip-flops to determine time spacing between transitions to perform a frequency comparison of the output signal relative to the input signal; extracting a clock from an input digital signal; and performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator.
摘要翻译：一种使用锁相环接收振荡输入信号并产生输出信号的方法，所述锁相环包括链接在一起的多个触发器，所述多个触发器包括具有第一触发器的第一触发器，第一输出，包括具有耦合到第一输出并具有第二输出的输入的第二触发器，并且包括具有耦合到第二输出的输入的第三触发器，所述锁相环还包括控制节点，方法，包括使用触发器来确定转变之间的时间间隔以执行输出信号相对于输入信号的频率比较; 从输入数字信号中提取时钟; 并执行相位控制和调节压控振荡器的控制节点上的电压。

26. 发明授权

US5774022A Digital clock recovery loop 失效
标题翻译：数字时钟恢复回路
公开(公告)号：US5774022A
公开(公告)日：1998-06-30
申请号：US707220
申请日：1996-08-29
申请人： Dan M. Griffin , George E. Pax , James E. O'Toole
发明人： Dan M. Griffin , George E. Pax , James E. O'Toole
IPC分类号： H03L7/089 , H03L7/113 , H04B1/707 , H04L7/033 , H03L7/10
CPC分类号： H03L7/113 , H03L7/0895 , H03L7/0896 , H04L7/033 , H04B1/707
摘要： A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit including a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.
摘要翻译：一种通信系统，包括从输入数字数据中提取时钟信号的时钟恢复电路，所述时钟恢复电路包括具有控制节点的压控振荡器，并具有产生具有响应于施加的电压而变化的频率的输出波的输出到控制节点; 电荷泵和环路滤波器电路，用于控制压控振荡器的控制节点上的电压变化率; 启动电路，执行频率检测，并结合电荷泵和环路滤波器电路调节压控振荡器的控制节点上的电压; 以及执行相位检测并调节压控振荡器的控制节点上的电压的状态机。

27. 发明授权

US5982237A Digital clock recovery loop 失效
标题翻译：数字时钟恢复回路
公开(公告)号：US5982237A
公开(公告)日：1999-11-09
申请号：US5090
申请日：1998-01-09
申请人： George E. Pax , James E. O'Toole , Dan M. Griffin
发明人： George E. Pax , James E. O'Toole , Dan M. Griffin
IPC分类号： H03L7/089 , H03L7/113 , H04B1/707 , H04L7/033 , H03L1/00 , H03L7/18
CPC分类号： H03L7/113 , H03L7/0895 , H03L7/0896 , H04L7/033 , H04B1/707
摘要： A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit comprising:a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.
摘要翻译：一种通信系统，包括从输入的数字数据中提取时钟信号的时钟恢复电路，所述时钟恢复电路包括：具有控制节点并具有产生具有响应于电压而变化的频率的输出波的输出的压控振荡器应用于控制节点; 电荷泵和环路滤波器电路，用于控制压控振荡器的控制节点上的电压变化率; 启动电路，执行频率检测，并结合电荷泵和环路滤波器电路调节压控振荡器的控制节点上的电压; 以及执行相位检测并调节压控振荡器的控制节点上的电压的状态机。

28. 发明授权

US4653074A Bit sync generator 失效
标题翻译：位同步发生器
公开(公告)号：US4653074A
公开(公告)日：1987-03-24
申请号：US694656
申请日：1985-01-24
申请人： Dan M. Griffin , Clifford T. Johnson , Larry J. Miller
发明人： Dan M. Griffin , Clifford T. Johnson , Larry J. Miller
IPC分类号： H04L7/033 , H04L7/00 , H03K5/135
CPC分类号： H04L7/0331
摘要： A system for synchronizing information bits to any frequency signal chain with low jitter correction and adapted for gate array implementation.
摘要翻译：一种用于将信息位同步到具有低抖动校正并适用于门阵列实现的任何频率信号链的系统。

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