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21. 发明申请

US20060059373A1 Integrated circuit chip for encryption and decryption using instructions supplied through a secure interface 审中-公开
标题翻译：使用通过安全接口提供的指令进行加密和解密的集成电路芯片
公开(公告)号：US20060059373A1
公开(公告)日：2006-03-16
申请号：US10938774
申请日：2004-09-10
申请人： Camil Fayad , John Li , Siegfried Sutter
发明人： Camil Fayad , John Li , Siegfried Sutter
IPC分类号： G06F12/14
CPC分类号： G06F21/82 , G06F12/1408 , G06F21/72
摘要： An integrated circuit chip is provided which contains one or more processors and one or more cryptographic engines. A flow control circuit having a command processor accepts requests and data via a secure external interface through which only encrypted information is passed. The flow control circuit mediates decryption of this information using one or more cryptographic keys passed to the command processor. The decrypted information is stored in a preferably volatile, on-chip memory in unencrypted form. The flow control circuit is then able to accept requests which invoke the stored, decrypted instructions. More specifically, the invoked instructions are usable to control the cryptographic engines present on the chip in ways knowable only to the one who provides the encrypted instructions. In this way, many different encryption algorithms are employable in a secure fashion.
摘要翻译：提供一种集成电路芯片，其包含一个或多个处理器和一个或多个加密引擎。具有命令处理器的流控制电路经由安全的外部接口接收请求和数据，通过该外部接口仅传递加密的信息。流控制电路使用传递给命令处理器的一个或多个加密密钥介入该信息的解密。解密的信息以未加密的形式存储在优选易失性的片上存储器中。流控制电路然后能够接受调用存储的解密指令的请求。更具体地，被调用的指令可用于以仅以提供加密指令的方式可知的方式来控制存在于芯片上的加密引擎。以这种方式，可以以安全的方式使用许多不同的加密算法。

22. 发明授权

US06978016B2 Circuits for calculating modular multiplicative inverse 有权
标题翻译：用于计算模数乘法逆的电路
公开(公告)号：US06978016B2
公开(公告)日：2005-12-20
申请号：US09740245
申请日：2000-12-19
申请人： Chin-Long Chen , Vincenzo Condorelli , Camil Fayad
发明人： Chin-Long Chen , Vincenzo Condorelli , Camil Fayad
IPC分类号： G06F7/52 , G06F7/72 , H04L9/30
CPC分类号： G06F7/723
摘要： The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design which includes a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations. A checksum mechanism is also provided to insure accurate operation without impacting speed and without significantly increasing complexity. While the present disclosure is directed to a complex system which includes a number of features, the present application is particularly directed to the incorporation and integration of circuits used for calculating a modular multiplicative inverse used as an input parameter to the process.
摘要翻译：在公开密钥加密和解密系统中使用的模幂运算功能是在独立的引擎中实现的，该独立引擎在其核心模乘法电路中分两个阶段工作，这两个阶段共享重叠的硬件结构。将硬件结构中的大阵列用于乘法和加法分割成更小的结构导致乘法器设计，其包括以链式方式链接在一起的一系列几乎相同的处理元件。作为分段处理元件的两相操作和链接在一起的结果，整体结构以流水线方式操作以提高生产量和速度。链式处理元件被构造成提供具有用于处理模量因子的单独部件的可分隔链。在这种模式下，该系统特别适用于利用中国剩余定理的特征进行快速求幂运算。还提供校验和机制以确保精确的操作而不影响速度并且不会显着增加复杂性。虽然本公开涉及包括许多特征的复杂系统，但是本申请特别涉及用于计算用作过程的输入参数的模乘法逆的电路的并入和集成。

23. 发明申请

US20050185791A1 CIRCUITS FOR CALCULATING MODULAR MULTIPLICATIVE INVERSE 有权
标题翻译：用于计算模块化多项式反演的电路
公开(公告)号：US20050185791A1
公开(公告)日：2005-08-25
申请号：US09740245
申请日：2000-12-19
申请人： Chin-Long Chen , Vincenzo Condorelli , Camil Fayad
发明人： Chin-Long Chen , Vincenzo Condorelli , Camil Fayad
IPC分类号： G06F7/52 , G06F7/72 , H04L9/30
CPC分类号： G06F7/723
摘要： The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations. A checksum mechanism is also provided to insure accurate operation without impacting speed and without significantly increasing complexity. While the present disclosure is directed to a complex system which includes a number of features, the present application is particularly directed to the incorporation and integration of circuits used for calculating a modular multiplicative inverse used as an input parameter to the process.
摘要翻译：在公开密钥加密和解密系统中使用的模幂运算功能是在独立的引擎中实现的，该独立引擎在其核心模乘法电路中分两个阶段工作，这两个阶段共享重叠的硬件结构。将硬件结构中的大阵列用于乘法和加法分割成更小的结构导致乘法器设计，其包括以链式方式链接在一起的一系列几乎相同的处理元件。作为分段处理元件的两相操作和链接在一起的结果，整体结构以流水线方式操作以提高生产量和速度。链式处理元件被构造成提供具有用于处理模量因子的单独部件的可分隔链。在这种模式下，该系统特别适用于利用中国剩余定理的特征进行快速求幂运算。还提供校验和机制以确保精确的操作而不影响速度并且不会显着增加复杂性。虽然本公开涉及包括多个特征的复杂系统，但是本申请特别涉及用于计算用作过程的输入参数的模乘法逆的电路的并入和集成。

24. 发明申请

US20060059369A1 Circuit chip for cryptographic processing having a secure interface to an external memory 审中-公开
标题翻译：用于密码处理的电路芯片具有与外部存储器的安全接口
公开(公告)号：US20060059369A1
公开(公告)日：2006-03-16
申请号：US10938835
申请日：2004-09-10
申请人： Camil Fayad , John Li , Siegfried Sutter
发明人： Camil Fayad , John Li , Siegfried Sutter
IPC分类号： G06F12/14 , H04L9/32 , G06F11/30
CPC分类号： G06F21/72 , G06F21/6218 , G06F21/79
摘要： A mechanism is provided in which a secure chip for performing cryptographic and/or other functions is able to securely access a separate random access memory externally disposed with respect to a secure chip boundary. Addressing of the external memory is controlled so as to define certain regions therein which receive and store only encrypted information from the chip. Other regions of the external memory are set aside for the receipt and storage of unencrypted information. Access to the external memory is provided through a controlled interface which communicates with internal chip hardware which operates to control the flow of communication between various internal components such as cryptographic engines, data processors, internal memory of both the volatile and the nonvolatile variety and an external interface which provides the only other access to the chip. The internal chip hardware with which the external memory interface communicates is implemented as a combined ASIC and programmable hardware circuit, wherein the programmable hardware circuit is also securely configurable.
摘要翻译：提供了一种机制，其中用于执行加密和/或其他功能的安全芯片能够安全地访问相对于安全芯片边界而外部设置的单独的随机存取存储器。控制外部存储器的寻址以便限定其中接收并存储来自芯片的加密信息的某些区域。留出外部存储器的其他区域用于接收和存储未加密的信息。通过与内部芯片硬件进行通信的受控接口提供对外部存储器的访问，该内部芯片硬件用于控制各种内部组件（例如密码引擎，数据处理器，易失性和非易失性品种的内部存储器）之间的通信流和外部接口，只提供对芯片的唯一访问。外部存储器接口通信的内部芯片硬件被实现为组合ASIC和可编程硬件电路，其中可编程硬件电路也可以可靠地配置。

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