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21. 发明授权

US06501671B2 Semiconductor memory device enabling selective production of different semiconductor memory devices operating at different external power-supply voltages 失效
标题翻译：半导体存储器件能够选择性地生产在不同外部电源电压下工作的不同半导体存储器件
公开(公告)号：US06501671B2
公开(公告)日：2002-12-31
申请号：US09793996
申请日：2001-02-28
申请人： Yasuhiro Konishi
发明人： Yasuhiro Konishi
IPC分类号： G11C506
CPC分类号： G11C5/147 , G11C5/14
摘要： Common circuit includes inactivation/activation circuits. Exclusive circuits include inverters IV3, IV4, IV5 and IV6 at the input portions thereof. When an SDR-SDRM is to be produced, inactivation/activation circuit outputs an inactivation signal DASL fixed to a ground voltage to exclusive circuit, while inactivation/activation circuit outputs a signal /OE inverted from an output enable signal OE to exclusive circuit. Inverters IV5 and IV6 in exclusive circuit then output a signal based on the signal /OE. Further, an N-channel MOS transistor and a P-channel MOS transistor in exclusive circuit are completely turned off, so that no through current flows from a power-supply node to a ground terminal in exclusive circuit. As a result, generation of the through current is prevented in an inactivated circuit.
摘要翻译：公共电路包括灭活/激活电路。专用电路在其输入部分包括反相器IV3，IV4，IV5和IV6。当要生成SDR-SDRM时，灭活/激活电路将固定为接地电压的失活信号DASL输出到专用电路，而灭活/激活电路将从输出使能信号OE反相的信号/ OE输出到专用电路。独占电路中的逆变器IV5和IV6然后基于信号/ OE输出信号。此外，专用电路中的N沟道MOS晶体管和P沟道MOS晶体管完全截止，从而在专用电路中，不会从电源节点流向接地端子。结果，在非激活电路中防止通过电流的产生。

22. 发明授权

US06477109B2 Synchronous semiconductor memory device allowing data to be satisfactorily rewritten therein 失效
标题翻译：允许在其中令人满意地重写数据的同步半导体存储器件
公开(公告)号：US06477109B2
公开(公告)日：2002-11-05
申请号：US09922669
申请日：2001-08-07
申请人： Kiyohiro Furutani , Yasuhiro Konishi
发明人： Kiyohiro Furutani , Yasuhiro Konishi
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/225 , G11C11/4076
摘要： In a SDRAM, there is introduced a control signal going active low following a passage of a predetermined period of time after a sense amplifier activation signal goes active high. When a signal going high during a burst period goes low and the control signal also goes low, a word line is dropped, non-selected low. As such, paired bit lines can have a potential difference sufficiently amplified to allow data to be satisfactorily rewritten into a memory cell.
摘要翻译：在SDRAM中，在读出放大器激活信号变为高电平之后经过预定时间段后引入控制信号变为有效低电平。当突发期间的信号变为高电平，并且控制信号也变低时，字线被丢弃，未选择为低电平。这样，成对的位线可以具有充分放大的电位差，以使数据能够令人满意地重写到存储单元中。

23. 发明授权

US06449198B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06449198B1
公开(公告)日：2002-09-10
申请号：US09717375
申请日：2000-11-22
申请人： Kei Hamade , Takeshi Hamamoto , Masaru Haraguchi , Yasuhiro Konishi
发明人： Kei Hamade , Takeshi Hamamoto , Masaru Haraguchi , Yasuhiro Konishi
IPC分类号： G11C700
CPC分类号： G11C7/1048 , G11C11/4096 , G11C11/4097
摘要： In the SDRAM, a selector selects one of four global IO line pairs according to a column block select signal and a word configuration selecting signal, and connects the selected global IO line pair to an input/output node pair of a preamplifier in a pulsed manner for a prescribed period of time. Since the equalization of the global IO line pair can be started immediately after the global IO line pair is connected in a pulsed manner to the input/output node pair of the preamplifier, longer equalization period for the global IO line can be set aside so that the read operation can be stabilized.
摘要翻译：在SDRAM中，选择器根据列块选择信号和字配置选择信号来选择四个全局IO线对中的一个，并将所选择的全局IO线对以脉冲方式连接到前置放大器的输入/输出节点对在规定的时间内。由于全局IO线对的均衡可以在全局IO线对以脉冲方式连接到前置放大器的输入/输出节点对之后立即开始，所以可以将全局IO线的更长的均衡周期放在一边，以便读取操作可以稳定。

24. 发明授权

US5818768A Operation mode setting circuit in semiconductor device 失效
标题翻译：半导体器件中的工作模式设定电路
公开(公告)号：US5818768A
公开(公告)日：1998-10-06
申请号：US767496
申请日：1996-12-16
申请人： Seiji Sawada , Yasuhiro Konishi
发明人： Seiji Sawada , Yasuhiro Konishi
IPC分类号： G11C11/401 , G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1045
摘要： A correspondence defining circuit changes a correspondence between an external signal and an internal signal and supplies it to a mode designating signal generating circuit according to a logic state of an operation mode switching signal. The mode designating signal generating circuit activates a mode designating signal which designates a specific operation mode in a semiconductor device when the internal signal satisfies a prescribed condition. An operation mode setting circuit, applicable to applications in which states of external signals are different without a change of its internal structure, is thus provided.
摘要翻译：对应定义电路改变外部信号和内部信号之间的对应关系，并根据操作模式切换信号的逻辑状态将其提供给模式指定信号发生电路。当内部信号满足规定条件时，模式指定信号发生电路激活指定半导体器件中的特定操作模式的模式指定信号。因此，提供了适用于其外部信号的状态不同而不改变其内部结构的应用的操作模式设定电路。

25. 发明授权

US5815462A Synchronous semiconductor memory device and synchronous memory module 失效
标题翻译：同步半导体存储器件和同步存储器模块
公开(公告)号：US5815462A
公开(公告)日：1998-09-29
申请号：US800905
申请日：1997-02-12
申请人： Yasuhiro Konishi , Hisashi Iwamoto , Takashi Araki , Yasumitsu Murai , Seiji Sawada
发明人： Yasuhiro Konishi , Hisashi Iwamoto , Takashi Araki , Yasumitsu Murai , Seiji Sawada
IPC分类号： G11C11/407 , G06F12/00 , G06F13/16 , G11C7/10 , G11C7/22 , G11C11/409 , G11C8/00
CPC分类号： G11C7/225 , G11C7/1039 , G11C7/1072 , G11C7/22
摘要： A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.
摘要翻译：用于控制外部信号的输入和用于控制内部操作的第一时钟信号和用于控制数据输出的第二时钟信号分别被施加到分离的时钟输入节点。可以调整相对于第一时钟信号的数据输出定时，从而可以调整时钟存取时间和数据保持时间。内部数据读取路径被流水线化以包括响应于第一时钟信号的第一传送门，用于传送内部读取数据和第二传送门，响应于第二时钟信号，用于从第一传送门传送内部读取数据，以便通过输出缓冲区。提供一种同步半导体存储器件，其能够根据应用和减少时钟存取时间将时钟访问时间和数据保持时间设置在最佳值。

26. 发明授权

US5796669A Synchronous semiconductor memory device 失效
标题翻译：同步半导体存储器件
公开(公告)号：US5796669A
公开(公告)日：1998-08-18
申请号：US900123
申请日：1997-07-25
申请人： Takashi Araki , Hisashi Iwamoto , Yasuhiro Konishi
发明人： Takashi Araki , Hisashi Iwamoto , Yasuhiro Konishi
IPC分类号： G11C11/407 , G11C11/406 , G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C7/1063
摘要： Switches (11, 12) select either of refresh address counters (6a, 6b) in accordance with a refresh bank set signal (.phi.REFADD) when a bank refresh signal (.phi.BANKREF) is activated. An internal bank address (int.BA) serves as the refresh bank set signal (.phi.REFADD) to control the switch (12) and the refresh address counter (6a or 6b) designated by the internal bank address (int.BA) performs a count operation in synchronization with a refresh clock (.phi.REFCLK). The switch (11) outputs either of refresh addresses (Ref.Add.sub.-- A , Ref.Add.sub.-- B ) which is updated. With this configuration provided is an SDRAM which allows access to data during a refresh operation.
摘要翻译：当bank刷新信号（phi BANKREF）被激活时，开关（11,12）根据刷新组设置信号（phi REFADD）来选择刷新地址计数器（6a，6b）。内部银行地址（int.BA）用作刷新组设置信号（phi REFADD）以控制开关（12），由内部银行地址（int.BA）指定的刷新地址计数器（6a或6b）执行计数操作与刷新时钟同步（phi REFCLK）。开关（11）输出更新的刷新地址（Ref.Add-A <0:10>，Ref.Add-B <0:10>）。提供这种配置是允许在刷新操作期间访问数据的SDRAM。

27. 发明授权

US5708611A Synchronous semiconductor memory device 失效
标题翻译：同步半导体存储器件
公开(公告)号：US5708611A
公开(公告)日：1998-01-13
申请号：US801889
申请日：1997-02-18
申请人： Hisashi Iwamoto , Yasuhiro Konishi
发明人： Hisashi Iwamoto , Yasuhiro Konishi
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/403 , G11C11/406 , G11C8/00
CPC分类号： G11C7/222 , G11C11/406 , G11C7/1072 , G11C7/22
摘要： A refresh control circuit of a DLL circuit responds to an auto refresh detection signal AR and a self refresh detection signal SR to inhibit input of clock signals ECLK and RCLK to a phase comparator and to a voltage control delay circuit. The DLL circuit can be stopped in a mode where an internal clock signal is not required to reduce power consumption.
摘要翻译： DLL电路的刷新控制电路响应自动刷新检测信号AR和自刷新检测信号SR，以禁止对相位比较器和电压控制延迟电路的时钟信号ECLK和RCLK的输入。可以以不需要内部时钟信号来降低功耗的模式停止DLL电路。

28. 发明授权

US5650968A Semiconductor memory device 失效
公开(公告)号：US5650968A
公开(公告)日：1997-07-22
申请号：US655322
申请日：1996-05-21
申请人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
发明人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
IPC分类号： G06F12/08 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/12 , G11C11/00 , G11C13/00
CPC分类号： G11C8/00 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G06F12/0893 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02B60/1225
摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

29. 发明授权

US5623454A Semiconductor memory device 失效
公开(公告)号：US5623454A
公开(公告)日：1997-04-22
申请号：US599265
申请日：1996-02-09
申请人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
发明人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
IPC分类号： G06F12/08 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/12 , G11C11/00 , G11C13/00
CPC分类号： G11C8/00 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G06F12/0893 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02B60/1225
摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

30. 发明授权

US5511029A Test circuit in clock synchronous semiconductor memory device 无效
标题翻译：时钟同步半导体存储器件中的测试电路
公开(公告)号：US5511029A
公开(公告)日：1996-04-23
申请号：US246582
申请日：1994-05-19
申请人： Seiji Sawada , Yasuhiro Konishi
发明人： Seiji Sawada , Yasuhiro Konishi
IPC分类号： G11C11/401 , G11C11/407 , G11C11/409 , G11C29/00 , G11C29/26 , G11C29/34 , G11C29/40 , G11C7/00
CPC分类号： G11C29/40 , G11C29/26
摘要： In order to reduce a test time for a synchronous type memory device, a compression circuit compresses a plurality of memory cell data which are inputted in a plurality of read registers provided for a data output terminal to 1-bit data. A bank selection circuit selects an output of the compression circuit of either a bank #A or a bank #B. A tristate inverter buffer passes the 1-bit compression data selected by the bank selection circuit in accordance with a test mode command signal. The data output terminal outputs compressed data of a plurality of bits of memory cells. Thus, it is possible to simultaneously determine pass/fail of a plurality of memory cells, thereby reducing the test time.
摘要翻译：为了减少同步型存储器件的测试时间，压缩电路将输入到数据输出端子的多个读寄存器中输入的多个存储单元数据压缩为1位数据。存储体选择电路选择存储体#A或存储体#B的压缩电路的输出。三态反相缓冲器根据测试模式命令信号传递由存储体选择电路选择的1位压缩数据。数据输出端输出多个位的存储单元的压缩数据。因此，可以同时确定多个存储单元的通过/失败，从而减少测试时间。

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