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21. 发明授权

US06184143B2 Semiconductor integrated circuit device and fabrication process thereof 失效
标题翻译：半导体集成电路器件及其制造工艺
公开(公告)号：US06184143B2
公开(公告)日：2001-02-06
申请号：US09123319
申请日：1998-07-28
申请人： Naofumi Ohashi , Hizuru Yamaguchi , Junji Noguchi , Nobuo Owada
发明人： Naofumi Ohashi , Hizuru Yamaguchi , Junji Noguchi , Nobuo Owada
IPC分类号： H07L2102
CPC分类号： H01L21/76862 , H01L21/31053 , H01L21/316 , H01L21/76819 , H01L21/76832 , H01L21/76834 , H01L21/76838 , H01L21/7684 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05025 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/11
摘要： In a semiconductor integrated circuit wherein an interlayer insulating film is formed over a semiconductor substrate having a semiconductor device formed thereover; and an interconnection embedded in an interconnection groove in the interlayer insulating film is formed by the deposition of a metal film such as copper and polishing by the CMP method, another interlayer insulating film over the interconnection and interlayer insulating film is formed to have a blocking film, a planarizing film and an insulating film. As the planarizing film, a film having fluidity such as SOG is employed.
摘要翻译：在半导体集成电路中，其中在其上形成有半导体器件的半导体衬底上形成层间绝缘膜; 并且通过沉积铜等金属膜并通过CMP法研磨嵌入在层间绝缘膜中的互连槽中的互连，在互连和层间绝缘膜上形成另一层间绝缘膜以具有阻挡膜平面化膜和绝缘膜。作为平坦化膜，使用具有SOG等流动性的膜。

22. 发明授权

US06864169B2 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件及半导体集成电路器件的制造方法
公开(公告)号：US06864169B2
公开(公告)日：2005-03-08
申请号：US10233475
申请日：2002-09-04
申请人： Junji Noguchi , Naofumi Ohashi , Kenichi Takeda , Tatsuyuki Saito , Hizuru Yamaguchii , Nobuo Owada
发明人： Junji Noguchi , Naofumi Ohashi , Kenichi Takeda , Tatsuyuki Saito , Hizuru Yamaguchii , Nobuo Owada
IPC分类号： H01L21/3205 , H01L21/02 , H01L21/28 , H01L21/321 , H01L21/3213 , H01L21/70 , H01L21/768 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/0217 , H01L21/02063 , H01L21/02074 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/3185 , H01L21/3212 , H01L21/32136 , H01L21/67115 , H01L21/68792 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76838 , H01L21/7684 , H01L21/76882 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
摘要翻译：在形成通过CMP将氧化硅膜39的互连槽40中的Cu互连46a至46e形成之后，然后进行清洗，每个氧化硅膜39和Cu互连46a至46e的表面被还原等离子体（氨等离子体）。然后，没有真空断裂，连续形成盖膜（氮化硅膜）。该方法使得可以提高通过镶嵌方法形成的铜互连的绝缘击穿电阻（可靠性）。

23. 发明授权

US06756679B2 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device 有权
公开(公告)号：US06756679B2
公开(公告)日：2004-06-29
申请号：US10233421
申请日：2002-09-04
申请人： Junji Noguchi , Naofumi Ohashi , Kenichi Takeda , Tatsuyuki Saito , Hizuru Yamaguchii , Nobuo Owada
发明人： Junji Noguchi , Naofumi Ohashi , Kenichi Takeda , Tatsuyuki Saito , Hizuru Yamaguchii , Nobuo Owada
IPC分类号： H01L2348
CPC分类号： H01L21/0217 , H01L21/02063 , H01L21/02074 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/3185 , H01L21/3212 , H01L21/32136 , H01L21/67115 , H01L21/68792 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76838 , H01L21/7684 , H01L21/76882 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

24. 发明授权

US06797609B2 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件及半导体集成电路器件的制造方法
公开(公告)号：US06797609B2
公开(公告)日：2004-09-28
申请号：US10233432
申请日：2002-09-04
申请人： Junji Noguchi , Naofumi Ohashi , Kenichi Takeda , Tatsuyuki Saito , Hizuru Yamaguchii , Nobuo Owada
发明人： Junji Noguchi , Naofumi Ohashi , Kenichi Takeda , Tatsuyuki Saito , Hizuru Yamaguchii , Nobuo Owada
IPC分类号： H01L214763
CPC分类号： H01L21/0217 , H01L21/02063 , H01L21/02074 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/3185 , H01L21/3212 , H01L21/32136 , H01L21/67115 , H01L21/68792 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76838 , H01L21/7684 , H01L21/76882 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
摘要翻译：在形成通过CMP将氧化硅膜39的互连槽40中的Cu互连46a至46e形成之后，然后进行清洗，每个氧化硅膜39和Cu互连46a至46e的表面被还原等离子体（氨等离子体）。然后，没有真空断裂，连续形成盖膜（氮化硅膜）。该方法使得可以提高通过镶嵌方法形成的铜互连的绝缘击穿电阻（可靠性）。

25. 发明申请

US20080138979A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路器件的半导体集成电路器件的制造方法
公开(公告)号：US20080138979A1
公开(公告)日：2008-06-12
申请号：US12018790
申请日：2008-01-23
申请人： Junji NOGUCHI , Naofumi Ohashi , Kenichi Takeda , Tatsuyuki Saito , Hizuru Yamaguchii , Nobuo Owada
发明人： Junji NOGUCHI , Naofumi Ohashi , Kenichi Takeda , Tatsuyuki Saito , Hizuru Yamaguchii , Nobuo Owada
IPC分类号： H01L21/4763
CPC分类号： H01L21/0217 , H01L21/02063 , H01L21/02074 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/3185 , H01L21/3212 , H01L21/32136 , H01L21/67115 , H01L21/68792 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76838 , H01L21/7684 , H01L21/76882 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
摘要翻译：在形成通过CMP将氧化硅膜39的互连槽40中的Cu互连46a至46e形成之后，然后进行清洗，氧化硅膜39和Cu互连46a至46e的表面是用还原等离子体（氨等离子体）处理。然后，没有真空断裂，连续形成盖膜（氮化硅膜）。该方法使得可以提高通过镶嵌方法形成的铜互连的绝缘击穿电阻（可靠性）。

26. 发明授权

US06815330B2 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件及半导体集成电路器件的制造方法
公开(公告)号：US06815330B2
公开(公告)日：2004-11-09
申请号：US10140112
申请日：2002-05-08
申请人： Junji Noguchi , Naofumi Ohashi , Kenichi Takeda , Tatsuyuki Saito , Hizuru Yamaguchii , Nobuo Owada
发明人： Junji Noguchi , Naofumi Ohashi , Kenichi Takeda , Tatsuyuki Saito , Hizuru Yamaguchii , Nobuo Owada
IPC分类号： H01L214763
CPC分类号： H01L21/0217 , H01L21/02063 , H01L21/02074 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/3185 , H01L21/3212 , H01L21/32136 , H01L21/67115 , H01L21/68792 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76838 , H01L21/7684 , H01L21/76882 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

27. 发明授权

US06797606B2 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device 有权
公开(公告)号：US06797606B2
公开(公告)日：2004-09-28
申请号：US10233469
申请日：2002-09-04
申请人： Junji Noguchi , Naofumi Ohashi , Kenichi Takeda , Tatsuyuki Saito , Hizuru Yamaguchii , Nobuo Owada
发明人： Junji Noguchi , Naofumi Ohashi , Kenichi Takeda , Tatsuyuki Saito , Hizuru Yamaguchii , Nobuo Owada
IPC分类号： H01L214763
CPC分类号： H01L21/0217 , H01L21/02063 , H01L21/02074 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/3185 , H01L21/3212 , H01L21/32136 , H01L21/67115 , H01L21/68792 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76838 , H01L21/7684 , H01L21/76882 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

28. 发明授权

US5244820A Semiconductor integrated circuit device, method for producing the same, and ion implanter for use in the method 失效
标题翻译：半导体集成电路装置及其制造方法以及该方法中使用的离子注入机
公开(公告)号：US5244820A
公开(公告)日：1993-09-14
申请号：US921988
申请日：1992-08-03
申请人： Tadashi Kamata , Mitsuharu Honda , Jun Sugiura , Nobuo Owada , Hizuru Yamaguchi
发明人： Tadashi Kamata , Mitsuharu Honda , Jun Sugiura , Nobuo Owada , Hizuru Yamaguchi
IPC分类号： H01L21/265 , H01L21/8242
CPC分类号： H01L21/26593 , H01L21/265 , H01L21/26506 , H01L21/26513 , H01L21/2652 , H01J2237/2001 , H01J2237/31701 , H01L27/10894 , Y10S148/083
摘要： The present invention relates to an ion implantation process in a wafer process for a semiconductor integrated circuit device. Particularly, according to the present invention, a shallow junction can be formed by performing the implantation of ion while holding a wafer to be processed at a low temperature.
摘要翻译：本发明涉及用于半导体集成电路器件的晶片工艺中的离子注入工艺。特别地，根据本发明，可以通过在保持待处理的晶片在低温下进行离子的注入来形成浅结。

29. 发明授权

US06326299B1 Method for manufacturing a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US06326299B1
公开(公告)日：2001-12-04
申请号：US09361989
申请日：1999-07-28
申请人： Yoshio Homma , Seiichi Kondo , Noriyuki Sakuma , Naofumi Ohashi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada
发明人： Yoshio Homma , Seiichi Kondo , Noriyuki Sakuma , Naofumi Ohashi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada
IPC分类号： H01L214763
CPC分类号： H01L21/3212 , C09G1/02 , H01L21/7684
摘要： In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.
摘要翻译：为了抑制在绝缘膜中形成的槽中以镶嵌法形成铜基合金镶嵌布线时在抛光期间在铜基合金层上发生的凹陷等的增加，下金属层的研磨速度设定为比其蚀刻速度快五倍以上，并且当上金属层13成为布线时，绝缘膜的抛光速率被设定为低于下金属层的抛光速率，下金属层 12成为屏障分别抛光。因此，对象镶嵌布线可以分别形成在绝缘层和每个金属层上的凹陷上较少的侵蚀。

30. 发明授权

US5234845A Method of manufacturing semiconductor IC using selective poly and EPI silicon growth 失效
标题翻译：使用选择性聚和EPI硅生长制造半导体IC的方法
公开(公告)号：US5234845A
公开(公告)日：1993-08-10
申请号：US859789
申请日：1992-03-30
申请人： Atsumi Aoki , Hizuru Yamaguchi , Nobuo Owada
发明人： Atsumi Aoki , Hizuru Yamaguchi , Nobuo Owada
IPC分类号： H01L21/205 , H01L21/285 , H01L21/316 , H01L21/331 , H01L21/76 , H01L29/10 , H01L29/732
CPC分类号： H01L29/66287 , H01L21/28525 , H01L29/1004 , H01L29/732 , Y10S438/969
摘要： Herein disclosed is an improved bipolar transistor manufacturing method which adopts an EBT (Epitaxial Base Transistor) structure using an SPESG (Selective Poly-and-Epitaxial-Silicon Growth) technique. Specifically, the method of manufacturing a bipolar transistor according to the present invention comprises the steps of: forming an isolation oxide layer to enclose an active region of a single crystal semiconductor substrate and to have a lower surface than that of the substrate of said active region; simultaneously forming a single crystal silicon layer over the substrate surface of said active region and a polycrystal silicon layer to become integral with said single crystal silicon layer over the surface of said isolation oxide layer by simultaneously growing silicon films over the substrate surface of said active region and the surface of said isolation oxide layer; and forming an active region of a semiconductor element in said single crystal silicon layer.
摘要翻译：本文公开了一种改进的双极晶体管制造方法，其采用使用SPESG（_Selectial _Poly-and-_Piaxial-_Silicon _Growth）技术的EBT（_Epitaxial _Base _Transistor）结构。具体地，根据本发明的制造双极晶体管的方法包括以下步骤：形成隔离氧化物层以包围单晶半导体衬底的有源区并具有比所述有源区的衬底的表面更低的表面 ; 同时在所述有源区的衬底表面上形成单晶硅层和多晶硅层，以在所述隔离氧化物层的表面上与所述单晶硅层成一体，通过在所述有源区的衬底表面上同时生长硅膜和所述隔离氧化物层的表面; 以及在所述单晶硅层中形成半导体元件的有源区。

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