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21. 发明授权

US07848170B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07848170B2
公开(公告)日：2010-12-07
申请号：US12407938
申请日：2009-03-20
申请人： Yoshihisa Sugiura
发明人： Yoshihisa Sugiura
IPC分类号： G11C5/14
CPC分类号： G11C16/30 , G11C5/02 , G11C5/143
摘要： A nonvolatile semiconductor memory has a first memory chip set so as to be operated by specifying the chip address upon reset; and a second memory chip set so as not to be specified by the chip address and not to be operated upon reset, the first memory chip and the second memory chip each comprising a power-on reset circuit which detects a power supply voltage after power-on and outputs a reset signal for resetting an operation when the power supply voltage is equal to or higher than a predetermined value.
摘要翻译：非易失性半导体存储器具有第一存储器芯片，以便通过在复位时指定芯片地址来操作; 以及第二存储器芯片，其不被芯片地址指定，并且在复位时不被操作，所述第一存储器芯片和第二存储器芯片各自包括检测电源电压之后的电源电压的上电复位电路，并且当电源电压等于或高于预定值时，输出用于复位操作的复位信号。

22. 发明授权

US07508725B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07508725B2
公开(公告)日：2009-03-24
申请号：US11668917
申请日：2007-01-30
申请人： Yoshihisa Sugiura , Atsushi Inoue
发明人： Yoshihisa Sugiura , Atsushi Inoue
IPC分类号： G11C7/00
CPC分类号： G11C29/16 , G11C16/04 , G11C29/40 , G11C2029/0405 , G11C2029/3602
摘要： A semiconductor memory device is disclosed, which includes a memory cell array including a plurality of memory cells, a built-in self-test circuit which writes test pattern data including binary 0 and binary 1 in the memory cells in units of a page to perform a test for the memory cells, a plurality of sense amplifiers which hold a plurality of data read from the memory cells in units of a page, and a detection circuit which collectively detects the plurality of data held by the sense amplifiers and outputs a detection result to the built-in self-test circuit.
摘要翻译：公开了一种半导体存储器件，其包括包括多个存储器单元的存储单元阵列，内置的自测电路，其将包含二进制0和二进制1的测试图形数据以页为单位写入到存储单元中用于存储单元的测试，以页为单位保存从存储单元读取的多个数据的多个读出放大器和共同检测由读出放大器保持的多个数据并输出检测结果的检测电路内置自检电路。

23. 发明申请

US20080175057A1 NON-VOLATILE SEMICONDUCTOR MEMORY 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20080175057A1
公开(公告)日：2008-07-24
申请号：US11854048
申请日：2007-09-12
申请人： Yoshihisa Sugiura , Takashi Suzuki
发明人： Yoshihisa Sugiura , Takashi Suzuki
IPC分类号： G11C16/00
CPC分类号： G11C16/349 , G11C16/0483 , G11C27/005
摘要： A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.
摘要翻译：公开了一种非易失性半导体存储器，其包括多个存储单元阵列，每个存储单元阵列具有分配给相应单元阵列的一部分的重写数量的存储区域，以及存储重写数量的写入控制电路通过以比普通写入电压低的电压执行数据写入到单元晶体管，在多个存储单元阵列的未选择的存储单元阵列中重写存储区域数量的单元晶体管中的重写次数，以便根据注入到单元晶体管的浮置栅极的电子量，以模拟方式改变单元晶体管的阈值。

24. 发明申请

US20070153582A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND NON-VOLATILE MEMORY SYSTEM USING THE SAME 有权
标题翻译：半导体集成电路器件及其非易失性存储器系统
公开(公告)号：US20070153582A1
公开(公告)日：2007-07-05
申请号：US11685391
申请日：2007-03-13
申请人： Atsushi Inoue , Yoshihisa Sugiura , Tatsuya Tanaka
发明人： Atsushi Inoue , Yoshihisa Sugiura , Tatsuya Tanaka
IPC分类号： G11C11/34
CPC分类号： G11C16/349
摘要： A semiconductor integrated circuit device includes a non-volatile memory having a pseudo pass function of returning a pass as a status even if a bit error reaching an allowable number of bits occurs after at least one of write or erase sequence is completed. The non-volatile memory includes an issue timing control section for controlling timing of issuing the pseudo pass function.
摘要翻译：半导体集成电路装置包括具有将通过作为状态返回的伪通函数的非易失性存储器，即使在完成了写入或擦除序列中的至少一个之后发生达到允许的位数的位错误。非易失性存储器包括用于控制发出伪通函数的定时的发行定时控制部分。

25. 发明申请

US20060098489A1 Semiconductor integrated circuit device and non-volatile memory system using the same 有权
公开(公告)号：US20060098489A1
公开(公告)日：2006-05-11
申请号：US11097300
申请日：2005-04-04
申请人： Atsushi Inoue , Yoshihisa Sugiura , Tatsuya Tanaka
发明人： Atsushi Inoue , Yoshihisa Sugiura , Tatsuya Tanaka
IPC分类号： G11C11/34
CPC分类号： G11C16/349
摘要： A semiconductor integrated circuit device includes a non-volatile memory having a pseudo pass function of returning a pass as a status even if a bit error reaching an allowable number of bits occurs after at least one of write or erase sequence is completed. The non-volatile memory includes an issue timing control section for controlling timing of issuing the pseudo pass function.

26. 发明授权

US06839276B2 Non-volatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US06839276B2
公开(公告)日：2005-01-04
申请号：US10455450
申请日：2003-06-06
申请人： Yoshihisa Sugiura , Takashi Suzuki
发明人： Yoshihisa Sugiura , Takashi Suzuki
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/34 , G11C27/00 , G11C16/00
CPC分类号： G11C16/349 , G11C16/0483 , G11C27/005
摘要： A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.
摘要翻译：公开了一种非易失性半导体存储器，其包括多个存储单元阵列，每个存储单元阵列具有分配给相应单元阵列的一部分的重写数量的存储区域，以及存储重写数量的写入控制电路通过以比普通写入电压低的电压执行数据写入到单元晶体管，在多个存储单元阵列的未选择的存储单元阵列中重写存储区域数量的单元晶体管中的重写次数，以便根据注入到单元晶体管的浮置栅极的电子量，以模拟方式改变单元晶体管的阈值。

27. 发明授权

US06512702B1 Non-volatile semiconductor memory device and data erase controlling method for use therein 失效
标题翻译：非挥发性半导体存储器件和数据擦除控制方法
公开(公告)号：US06512702B1
公开(公告)日：2003-01-28
申请号：US09539212
申请日：2000-03-30
申请人： Toshio Yamamura , Yoshihisa Sugiura , Kazuhisa Kanazawa , Koji Sakui , Hiroshi Nakamura
发明人： Toshio Yamamura , Yoshihisa Sugiura , Kazuhisa Kanazawa , Koji Sakui , Hiroshi Nakamura
IPC分类号： G11C1604
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/16 , G11C16/344
摘要： A memory cell array is divided into left and right cell arrays, each of which includes a plurality of blocks. Data erase is sequentially controlled by an erase control circuit on the basis of an erase command flag incorporated into a command register and an address incorporated into an address register. Batch erase is carried out with respect to selected blocks of the right and left cell arrays. After data erase, a verify operation is carried out with respect to the erased blocks by retrieving the erased blocks simultaneously with respect to the right and left cell arrays in parallel. Thus, the time required to retrieve the selected blocks for the verify operation after data erase is shortened, so that the time required to carry out the whole data erase is shortened.
摘要翻译：存储单元阵列被分成左和右单元阵列，每个阵列中的每一个包括多个块。基于结合到命令寄存器中的擦除命令标志和结合到地址寄存器中的地址，由擦除控制电路依次控制数据擦除。相对于右和左单元阵列的选定块执行批量擦除。在数据擦除之后，通过并行地相对于左和右单元阵列同时检索擦除块来执行关于擦除块的验证操作。因此，缩短在数据擦除之后检索用于验证操作的所选块所需的时间，从而缩短了执行整个数据擦除所需的时间。

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